Specifications

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D:\D\inter61a\INTERRUP.A Saturday, January 08, 2011 11:31 AM

05h 4 BYTEs sequencer registers

09h BYTE sequencer register 0

0Ah 25 BYTEs CRTC registers 0-8

23h 16 BYTEs palette registers 00h-0Fh

33h 4 BYTEs attribute registers 10h-13h

37h 9 BYTEs graphics controller registers 0-8

40h BYTE CRTC base address (low)

41h BYTE CRTC base address (high)

42h BYTE plane 0 latch

43h BYTE plane 1 latch

44h BYTE plane 2 latch

45h BYTE plane 3 latch

Format of VGA DAC state:

Offset Size Description (Table 00050)

00h BYTE read/write mode DAC

01h BYTE pixel address

02h BYTE pixel mask

03h 768 BYTEs color data (256 triples)

303h BYTE color select register

--------J-101D-------------------------------

INT 10 - VIDEO - DOS/V - SHIFT STATUS LINE CONTROL

AH = 1Dh

AL = function

00h enable shift status line(s)

BX = number of lines to reserve at bottom of screen (usu. 1)

01h disable shift status line

BX = number of lines reserved at bottom of screen (usually 1)

02h get number of status lines

Return: BX = number of lines reserved for shift status

SeeAlso: AH=19h

--------V-101D-------------------------------

INT 10 - SpeedSTAR Plus BIOS v4.23+ - SET SYNC PARAMETERS

AH = 1Dh

AL = video mode

ES = caller's segment

Return: nothing

Note: the caller's segment contains at offset 5Ch (FCB field in PSP)

or 100h a table with sync parameters (see #00051) (BIOS looks at both

offsets)

-102-

http://www.foxitsoftware.com For evaluation only.