User`s manual

1.4 Stereo analysis

The STOC board runs an optimized version of the SRI Small Vision

System (SVS) stereo algorithms. This version produces the same results as

SVS running on a standard PC, but is implemented inside the stereo device

on a small reconfigurable processor, called a Field Programmable Gate

Array (FPGA). The use of the FPGA frees up the host PC from the

expensive stereo calculations, and makes it available for all of the user’s

application code.

Figure 1-1 shows typical results from SVS and the STOC device. On the

left is one of the input images from the stereo cameras. The stereo images

are processed to produce a range image, also called a disparity image,

which encodes the distance to each pixel in the image, based on

triangulating matched regions in the left and right images. In the disparity

image, brighter areas indicate pixels that are closer. From the disparity

image, the 3D structure of objects can be re-created, as in the two images

on the right.

The STOC device comes pre-calibrated, so that lens distortions are

automatically removed from the images (the results are called

rectifiedimages). There is no need to perform any calibration steps – the

STOC is ready to start producing range results out of the box. However,

you may want to change the lenses at some point, and the device can easily

be recalibrated in the field, just like other Videre stereo devices.

More information about the stereo processing algorithm can be found in the

technical pages for SVS, at

www.ai.sri.com/~konolige/svs.

Figure 1-1 Stages in STOC processing. Left is one of the input images from the stereo imagers. The other two images show different 3D views

reconstructed from the disparity data.