Specifications

Technical Description
The PFC MegaPAC-EL and PFC MegaPAC-HPEL chassis consists of an off-line single phase, power-factor-cor-
rected front end, EMI filter, cooling fan, low noise filters, customer interface and associated housekeeping circuits.
Input AC mains voltage (L1, L2 and GND) is applied to a terminal block. The input current is passed through an
EMI filter designed to meet conducted noise limit “B” specifications of FCC Part 15, VDE 0871, and EN55022
class "B." At start-up, inrush current is limited by a PTC thermistor. The PTC is shunted out shortly after initial
power-up by a DC bus voltage Sense circuit driving a relay. After rectification, the input voltage is put through a
boost converter that keeps the AC input current sinusoidal and synchronized with the AC input voltage (in compli-
ance with EN61000). The boost converter delivers regulated high voltage DC to the hold-up capacitors and back-
plane. The backplane supplies power to a variety of ConverterPAC assemblies that provide the desired regulated
outputs.
Voltage conversion in the output assemblies is achieved by Vicor’s family of Zero-Current-Switching (ZCS) DC to
DC converters. These are forward converters in which the main switching element switches at zero current. This
patented topology has a number of unique attributes: low switching losses; high frequency operation resulting in
reduced size for magnetics and capacitors; excellent line and load regulation; wide adjustment range for output;
low EMI/RFI emissions and high efficiencies.
At initial power-up the PFC MegaPAC-EL and PFC MegaPAC-HPEL outputs are disabled to limit the inrush cur-
rent and to allow the DC bus potential to settle out to the correct operating level. A low-power flyback converter
operating with PWM current-mode control converts the high voltage DC bus into regulated low voltage to power
the internal housekeeping circuits and DC cooling fan. The internal housekeeping Vcc comes up within 2 s after
the application of input power. Once the high voltage bus is within its limits, the AC OK signal asserts to a TTL
“1” indicating the input power is OK, and enables the power outputs. An auxiliary Vcc output of 5 Vdc sourcing
up to 0.3A is provided for peripheral use.
An output Enable/Disable function is provided by using an optocoupler to control the Gate In pins of the
ConverterPAC assemblies. If the Enable/Disable control pin is pulled low, the optocoupler turns on, pulling the
Gate In pin low and disabling the ConverterPAC output. The nominal delay for an output to come up when meas-
ured from release of the Enable/Disable pin is 10-15 ms. The General Shutdown function controls all outputs
simultaneously and works in a similar manner.
The ride-through (holdup) time is the amount of time the load can be supported before loss of output regulation
after the loss of input power. Detecting the loss of input power takes a finite time period after which the AC Power
OK signal goes from a TTL “1” to “0." This signal is available for use within 1.2 seconds after initial power-up
and can be used to indicate an impending loss of power. At least 3 ms of warning time is given. Following the loss
of input power, the outputs are disabled when the bus voltage drops below its operating threshold.
Rev. 6/2004 Vicor 800-735-6200 Westcor Division 408-522-5280 Applications Engineering 800-927-9474 Pg. 5
PFC MegaPAC-EL/PFC MegaPAC-High Power Low Noise
Line Filter
Rectifier
Soft Start
Circuit
Boost Converter
PFC Control
E/D Control
QPAC #1
QPAC #2
QPAC #3
QPAC #8
Fan
Housekeeping
Power
Current
Monitor
Customer
Interface
Power
Output
Power
Output
Power
Output
Power
Output
Input
High Voltage
DC Bus
Enable/Disable Control
Current
Sample
Waveform
Sample
Figure 1. PFC MegaPAC-EL and PFC MegaPAC-HPEL Low Noise Architecture