Specifications

Output Sequencing
Using the MegaPAC's standard Input Interface Connector (J10) along with the ConverterPAC's optional DC OK
Option*, it is possible to implement unique output voltage power up and power down sequences. Below is an exam-
ple showing how this may be done.
* DC OK Option is not available for 1st Generation dual output DualQPACs
Requirement: 5V must start before the 3.3V output. If the 5V output is lost, the 3.3V output must turn off.
The first step in meeting this require-
ment is to configure the 5V QPAC with
the DC OK Option, which is indicated
by a "D" designator in the QPAC's part
number, located on the top surface of
each QPAC above the +Vout. Any
QPAC that has the DC OK option will
also have the 4 pin J3 DC OK connector
installed. To order a QPAC with the DC
OK option, please contact Westcor's
customer service department for assis-
tance. The DC OK option monitors the
output voltage of a given ConverterPAC
and provides a TTL logic signal depending
on its output voltage.
Figure 3 shows the correct wiring connections between the Power Good Connector (J3) of a 5V QPAC and the Input
Interface Connector (J10) of a typical PFC MegaPAC-EL configuration. In this example, the 3.3V QPAC is located
in the slot #7 and the 5V QPAC (with the DC OK option) is located in slot #8. In order for the Power Good option
to properly function, it requires a 5V source to provide the necessary Vcc pull up. This 5V source is conveniently
available using the +5V aux source from the Input Interface Connector (J10-9 and J10-10). With a Vcc voltage prop-
erly applied to the 5V QPAC's Power Good Connector (J3-1 and J3-4), the Power Good signal (J3-3) can now be con-
nected to the Enable/Disable control pin for slot #7 (J10-7). The 5V QPAC's Power Good signal will remain low
until its output has reached approximately 95% of its nominal output voltage. This will keep the 3.3V output in dis-
abled mode, allowing the 5V output to reach regulation first. In addition, should the 5V output drop below 85% the
Power Good signal will drop low and disable the 3.3V output. Figure 4 and 5 show the startup and shutdown wave-
forms for the circuit shown in Figure 3.
Rev. 6/2004 Vicor 800-735-6200 Westcor Division 408-522-5280 Applications Engineering 800-927-9474 Pg. 23
PFC MegaPAC-EL/PFC MegaPAC-High Power Low Noise
J2 Pin 1
J3 pin 1 (DC OK Option)
+ Vout
- Vout
Vtrim Pot Adjust (Option)
4
3
2
1
J3
J3-4 Vcc
J3-3 Power Good
J3-2 Power Good Inverted
J3-1 Si
g
nal Gro
und
Pin
DC OK (Power Good)
5V with "D" o
p
tion
(
DC OK
)
12345678
3.3V Output
1
12
2
11
3
10
4
9
5
8
6
7
L
1
L
2
Figure 1. QPAC Pinout
Figure 2. J3 DC OK Connector
Figure 3. Output Sequencing Wire Interconnect