Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -93- VGA Extended Registers
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
CR38 – Pixel Bus Mode .....................................................RW
7-6 Reserved .........................................always reads 0
5 Packed 24-Bit True-Color Mode
0 Disable ................................................... default
1 Enable
4 Standard VGA Mode in 64-Bit Configuration
0 Disable ................................................... default
1 Enable
3 True Color Mode
0 Disable ................................................... default
1 Enable
2 High Color Mode
0 Disable ................................................... default
1 Enable
1 Reserved .........................................always reads 0
0 16-Bit Pixel Bus
0 Disable ................................................... default
1 Enable
This register is protected by SRE_New[7]
CR39 – PCI Interface Control ..........................................RW
7 Pixel Data Format
0 Little Endian........................................... default
1 Big Endian
6-5 Memory Data with Big Endian Format
00 Pass Through (PT) ................................. default
01 Word Swap (WS)
10 Half Swap (HS)
11 Full Swap (FS)
4-3 BE[3-0]# With Big Endian Format
00 Pass Through (PT) ................................. default
01 Word Swap (WS)
10 Half Swap (HS)
11 Full Swap (FS)
2 PCI Burst Write
0 Disable ................................................... default
1 Enable
1 PCI Burst Read
0 Disable ................................................... default
1 Enable
0 MMIO Control
0 Disable ................................................... default
1 Enable (64KB VGA I/O space can be
memory mapped within the 4GB memory
space)
This register is protected by SRE_New[7]
CR3A – Physical Address Control ...................................RW
7 Reserved ......................................... always reads 0
6 AGP / PCI Select
0 PCI ......................................................default
1 AGP
5 Both IO
0 Disable ....................................................default
1 Enable
4 Memory Address Linearization
0 Disable ....................................................default
1 Enable
3 Reserved ......................................... always reads 0
2 AGP Software Reset
0 Normal ....................................................default
1 Reset
1 PCI Configuration Subsystem ID Write
0 Disable ....................................................default
1 Enable
0 Enhanced Register I/O Scheme
0 Disable ....................................................default
1 Enable
CR3B – Clock and Tuning ................................................RW
7 Observe Clock Source
0 VCLK1 ...................................................default
1 VCLK2
6-4 Clock Source Mode Select
0xx Internal Clock Chip
000 V/MCLK test mode, observe MCLK
001 V/MCLK test mode, observe VCLK1
010 V/MCLK test mode, observe VCLK2
011 Normal operation
1xx External Clock Chip
Bit 6 default is set from MA7
Bits 5-4 default is set from MA8,2 inverted
3 Clock Control
0 When bits 6-4 = 00x, clock is normal ....default
1 When bits 6-4 = 00x, clock is divided by 2
2-1 Reserved .........................................always reads 0
0 Vertical Retrace Memory Refresh
0 Disable
1 Enable....................................................default
This register is protected by SRE_New[7]
CR3C – Miscellaneous Control ........................................RW
7-3 Same Definition as GRF[7-3]................... default = 0
2 Reserved ......................................... always reads 0
1 Same Definition as GRF[1]...................... default = 0
0 Mode Select 1 ............................................ default = 0
0 This register has no function ..................default
The original GRF[7-0] bits are used
1 GRF[7-3, 1] accessed via this register only
GRF[2, 0] accessed at original register only
Original GRF[3] is R/W but has no function
This register is protected by SRE_New[7]