Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -92- VGA Extended Registers
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
CR2B – Horizontal Parameter Overflow.........................RW
7-5 Reserved .........................................always reads 0
4 Horizontal Blank Start Bit-8....................default = 0
3 Horizontal Retrace Start Bit-8 ...............default = 0
2 Horizontal Interlace Parameter Bit-8 ....default = 0
1 Horizontal Display Enable Bit-8 ............default = 0
0 Horizontal Total Bit-8 .............................default = 0
CR2D – GE Timing Control..............................................RW
7-5 Reserved .........................................always reads 0
4-3 GE Sample Clock Delay Selection...........default = 0
2-0 GE Frame Buffer Read Delay Cycles .....default = 0
CR2F – Performance Tuning............................................RW
7 Reserved .........................................always reads 0
6 DRAM Refresh Cycle Control Bit-1
(Bit-0 is CR11[6])
00 3 refresh cycles per horizontal line
01 5 refresh cycles per horizontal line
10 1 refresh cycles per horizontal line
11 2 refresh cycles per horizontal line
5 Blank TimingSelect
0 Normal blank.......................................... default
1 Blank is the inverse of display enable
4 Display FIFO Depth Control
0 32 deep ................................................... default
1 8 deep
3-2 Memory Read Ready Control
00 -reserved................................................. default
01 Fast read cycle (same as 10)
10 Fast read cycle (same as 01)
11 Normal read cycle
1 Clock Source
0 VCLK2
1 VCLK1 .................................................. default
0 Pin Scan (Test Only).................................default = 1
CR35-34 – Graphics Engine I/O Linear Address Base..RW
15-0 Graphics Engine Linear Address Base... default = 0
CR36 – Graphics Engine / Video Engine Control ..........RW
7 Graphics Engine
0 Disable ....................................................default
1 Enable
6 PCI Video Minifier
0 Bypass.....................................................default
1 Go through minifier
5 Video Aperture
0 Disable ....................................................default
1 Enable
4 Graphics Engine Software Reset
Writing a one to this bit resets the graphics engine
3 Graphics Engine I/O
0 Disable ....................................................default
1 Enable
2 String Write
0 Disable ....................................................default
1 Enable
1-0 Graphics Engine Register Mapping
00 I/O mapped at 21xxh ..............................default
01 Memory mapped at B7Fxxh
10 Memory mapped at BFFxxh
11 Memory mapped using the GE base register
CR37 – I
2
C / SMB Control................................................RW
7 SMBCLK Buffer is Open Drain........always reads 1
6 I
2
C SMBCLK Status ............................................RO
5-4 Reserved .........................................always reads 0
3 I
2
C Operation
0 Read ......................................................default
1 Write
2 Reserved ......................................... always reads 0
1 I
2
C SMBCLK Signal
0 Low
1 High .....................................................default
0 I
2
C SMBDAT Signal
0 Low ......................................................default
1 High