Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -91- VGA Extended Registers
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
CR1F – Software Programming.......................................RW
7-4 Reserved .........................................always reads 0
3-0 Display Memory Size
0011 1MB
0111 2MB
1111 4MB
0100 8MB
All other codes are reserved
Memory size is automatically detected during system setup.
CR20 – Command FIFO....................................................RW
7-6 Reserved .........................................always reads 0
5 Write Buffer
0 Disable .................................................... defaul
1 Enable
4 16-Bit Planar Mode
0 Disable .................................................... defaul
1 Enable
3-0 Reserved .........................................always reads 0
CR21 – Linear Addressing ................................................RW
7-6 Reserved .........................................always reads 0
5 Linear Memory Access
0 Disable .................................................... defaul
1 Enable
4-0 Reserved .........................................always reads 0
This register is write protected by SRE_New[7].
CR22 – CPU Latch Readback........................................... RO
7-0 Latched Data
Pointed to by GR4 (VGA Read Map Select Register
)
CR24 – VGA Attribute State ............................................ RO
7 VGA Attribute State
0 Index ...................................................... defaul
1 Data
6-0 Reserved .........................................always reads 0
CR25 – RAMDAC Read/Write Timing ...........................RW
7 PCLK / P[7-0] BufferTristate Control
0 Enable...................................................... defaul
1 Disable
6-4 Reserved .........................................always reads 0
3-0 RAMDAC Read / Write Wait States .....def =1111b
CR27 – CRT High Order Start Address..........................RW
7 Vertical Total Bit-10 .................................default = 0
6 Vertical Blanking Start Bit-10 ................default = 0
5 Vertical Retrace Start Bit-10 ..................default = 0
4 Vertical Display Enable End Bit-10 .......default = 0
3 Line Compare Bit-10 ...............................default = 0
2-0 Start Address Bits 19-17 ..........................default = 0
CR29 – RAMDAC Mode...................................................RW
7 External DAC
0 Disable .....................................................defaul
1 Enable
6 Reserved ......................................... always reads 0
5-4 CRTC Offset[9:8] for High or True Color Modes
3 GE I/O Decode
0 Disable .....................................................defaul
1 Enable
2 RAMDAC
0 External....................................................defaul
1 Internal
1-0 RS[3-2] for RAMDAC (if register access definition
is selected)
This register is write protected by SRE_New[7]
CR2A – Interface Select ....................................................RW
7 Reserved ......................................... always reads 0
6 Internal Data Path Width
0 8/16-bit.....................................................defaul
1 32-bit
5 Reserved ........................................always reads 1
4 Power Down Mode Using ROMCS#
0 Enable ......................................................defaul
1 Disable
3-0 Reserved .........................................always reads 0
This register is write protected by SRE_New[7]