Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -77- VGA Extended Registers
Technologies, Inc.
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Graphics Signature Analyzer Registers
SR21 – Signature Control..................................................RW
7 Signature Generator Enable
0 Disable (readback 0 indicates done)...... default
1 Enable (readback 1 indicates busy)
6 Signature Source Select
0 TV / CRT ............................................... default
1 LCD
5-0 Bit Select ...............................................default = 0
SR23-22 – Signature Data.................................................. RO
15-0 Signature Data
Graphics Power Management Control Registers
SR24 – Power Management Control................................RW
7 RAMDAC Clock During RAMDAC Powerdown
0 14.318 MHz .......................................... default
1 14.31818 MHz divided by 2
6 Enable VCLK2 VCO Directly
(without warmup sequence)
0 Enable
1 Don’t Enable .......................................... default
5-4 Clock Input Divisor
Divisor for 14.318 MHz clock input to MCLK to
drive DRAM refresh cycles in power managed
modes.
00 1 ..................................................... default
01 2
10 4
11 8
3 Power Management Slow MCLK
0 Use divided MCLK during standby &
suspend
1 Use MCLK during standby & suspend........def
2 Enable MCLK VCO Directly
(without warmup sequence)
0 Enable
1 Don’t Enable ......................................... default
1 Enable MCLK VCO Directly
(without warmup sequence)
0 Enable
1 Don’t Enable ......................................... default
0 DAC Power
0 Off ..................................................... default
1 On
Graphics Connector Control Registers
SR25 – Monitor Sense.........................................................RO
7-3 Reserved ......................................... always reads 0
2-0 Monitor Sense Result: [red, green, blue]
SR37 – Video Key Mode....................................................RW
7 Feature Connector Input Clock Polarity
0 Normal ....................................................default
1 Inverted
6 Signal Output (AFC Processing)
0 Signal output is sent before AFC processingdef
1 Signal output is sent after AFC processing
5-4 Feature Connector Input Pixel Clock Tuning
00 0 ns ......................................................default
01 4 ns
10 8 ns
11 12 ns delay of pixel clock with respect to data
3-0 Overlay Key Type
0000 VGA Port Only.......................................default
0001 Color Key & Video Key
0010 Color Key & not Video Key
0011 Color Key
0100 Not Color Key & Video Key
0101 Video Key
0110 Color Key XOR Video Key
0111 Color Key | Video Key
1000 Not Color Key & Not Video Key
1001 Color Key XNOR Video Key
1010 Not Video Key
1011 Color Key | Not Video Key
1100 Not Color Key
1101 Not Color Key | Video Key
1110 Not Color Key | Not Video Key
1111 Video Port Only
SR38 – Advanced Feature Connector (AFC) Control ...RW
7 Reserved ......................................... always reads 0
6 DCLK Rate (set after other bits for syncronization)
0 PCLK ......................................................default
1 PCLK / 2
5 DCLK Phase Select (if bit-6 = 1)
0 180 degree phase shift ............................default
1 In phase
4 DCLK Output Polarity
0 Normal when bit-6 = 0............................default
1 Inverted
3 VCLK Input Polarity
0 Normal ....................................................default
1 Inverted
2-1 Reserved ......................................... always reads 0
0 Pixel Data Bus Output Enable Control
0 Disable Output Drive..............................default
1 Disable drive only when EVIDEO# is low