Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -74- VGA Extended Registers
Technologies, Inc.
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VGA Extended Registers – Sequencer Indexed
SR8 – Old / New Status...................................................... RO
7 Old / New Status (see SRB, SRC, SRD, SRE, GRE)
0 Old ..................................................... default
1 New
6 Interlace Scan Field
0 Odd ..................................................... default
1 Even
5 Reserved .........................................always reads 0
4 Command FIFO Empty
0 Empty ..................................................... default
1 Not Empty
3-0 Reserved .........................................always reads 0
SR9 – Graphics Controller Version.................................. RO
7-0 Version Number..............................always reads 58h
SRB – Version / Old-New Mode Control.........................RW
7-0 Graphics Controller Version # ......always reads F3h
A write to this register will change the Old / New Mode
Control registers (SRD, SRE, and GRE) to the “old”
definition. A read from this register will change the Old /
New Mode Control registers to the “new” definition.
SRC – Configuration Port 1..............................................RW
Access to this register is enabled by SRE_Old[5] = 1 (“Select
Configuration Port 1”) and writes are enabled by SRE_New[7]
= 1 (“Configuration Port Write Enable”).
7 Reserved ....................................... always reads 1
6 Memory Bus Width
0 32-bit Memory Bus................................ default
1 64-bit Memory Bus
Note: Although the PLE133 integrated graphics
controller does not control memory directly (the
system memory controller is used to access graphics
memory as a portion of system memory), some
functional blocks in the graphics controller (such as
video) use this bit to manage their data bus widths.
5 Reserved ....................................... always reads 1
4 Video Subsystem Enable
0 46E8
1 3C3 ..................................................... default
3 Video BIOS Size
0 64K ..................................................... default
1 32K
2-0 Reserved ................................. always reads 111b
SRC – Configuration Port 2..............................................RW
Access to this register is enabled by SRE_Old[5] = 0 (“Select
Configuration Port 2”) and writes are enabled by SRE_New[7]
= 1 (“Configuration Port Write Enable”).
7-0 Reserved for BIOS
SRD – Mode Control 2 (Old) ............................................RW
7-6 Reserved .........................................always reads 0
5 Reserved ........................................always reads 1
4 Reserved .........................................always reads 0
3 CPU Bandwidth Select
0 Normal ....................................................default
1 Non-interrupted CPU access during VBLANK
2-0 Reserved .........................................always reads 0
SRD – Mode Control 2 (New)...........................................RW
7-4 Display FIFO Memory Request Threshold Ctrl
0000 Empty 0 level
0001 Empty 4 level..........................................default
0010 Empty 8 lrevel
0011 Empty 12 level
0100 Empty 16 level
0101 Empty 20 level
0110 Empty 24 level
0111 Empty 28 level
1000 Empty 32 level
1001 Empty 36 level
1010 Empty 40 level
1011 Empty 44 level
1100 Empty 48 level
1101 Empty 52 level
1110 Empty 56 level
1111 Empty 60 level
3 Reserved .........................................always reads 0
2-1 Video Clock Divide
00 Divide by 1..............................................default
01 Divide by 2
10 Divide by 4
11 Divide by 1.5
0 Reserved .........................................always reads 0