Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -2- Product Features
Technologies, Inc.
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• Internal Accelerated Graphics Port (AGP) Controller
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AGP v1.0 compliant
− Pipelined split-transaction long-burst transfers up to 533 MB/sec
− Eight level read request queue
− Four level posted-write request queue
− Thirty-two level (quadwords) read data FIFO (128 bytes)
− Sixteen level (quadwords) write data FIFO (64 bytes)
− Intelligent request reordering for maximum AGP bus utilization
− Supports Flush/Fence commands
− Graphics Address Relocation Table (GART)
− One level TLB structure
− Sixteen entry fully associative page table
− LRU replacement scheme
− Independent GART lookup control for host / AGP / PCI master accesses
− Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport driver support
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• Concurrent PCI Bus Controller
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PCI bus is synchronous / pseudo-synchronous to host CPU bus
− 33 MHz operation on the primary PCI bus
− Supports up to five PCI masters
− Peer concurrency
− Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time
− Zero wait state PCI master and slave burst transfer rate
− PCI to system memory data streaming up to 132Mbyte/sec
− PCI master snoop ahead and snoop filtering
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Six levels (double-words) of CPU to PCI posted write buffers
− Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities
− Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
− Forty-eight levels (double-words) of post write buffers from PCI masters to DRAM
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Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters
− Supports L1/L2 write-back forward to PCI master read to minimize PCI read latency
− Supports L1/L2 write-back merged with PCI master post-write to minimize DRAM utilization
− Delay transaction from PCI master reading DRAM
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Read caching for PCI master reading DRAM
− Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)
− Symmetric arbitration between Host/PCI bus for optimized system performance
− Complete steerable PCI interrupts
− PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs