Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -61- Graphics Accelerator PCI Bus Master Registers
Technologies, Inc.
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Graphics Accelerator AGP Registers
The default base I/O address for the AGP registers is 2300h.
The AGP control unit has 3 channels. These channels can
work independently and in parallel. Each channel has its own
capabilities:
Channel 0: Execution mode texture access.
Channel 1: Command List Operation. Executes command
lists from AGP memory.
Channel 2: Data Move. Moves data from AGP memory to
framebufferortotheCapture/MPEG2FIFO.
Also moves data from the frame buffer to AGP
memory.
Graphics AGP Configuration Registers
Port 2304 – Graphics AGP Capability List.....................RW
31-0 xx
Port 2334 – Graphics AGP Capability List Address......RW
31-0 xx
Graphics AGP Operation Registers
Port 2340 – Graphics AGP FB Command List Start .....RW
31-19 Reserved .........................................always reads 0
18-0 Frame Buffer Command List Start Address
Port 2344 – Graphics AGP FB Command List Size.......RW
31-19 Reserved .........................................always reads 0
18-3 Frame Buffer Command List Size (in quadwords)
Value programmed is the desired size minus one
2-0 Reserved .........................................always reads 0
Command List Format
The command list is stored in AGP memory in groups. Each
group has the following format:
Bit Bit
QuadWord
63 48 32 31 16 0
0 Data 0 Header
1Data2Data1
2Data4Data3
………
n/2+1 Pad/Datan-1 Datan–1/2
The header is a 32-bit word that contains information about
this group, such as the amount of useful data in the group. A
group is always padded to a quadword boundary. Padding
DWORDs are discarded by the channel. The format of the
header is as follows:
31 Consecutive Addressing
0 Disabled (all data in this group will be written
to the register with the destination address
specified in the “ADDR” field in bits 29-8)
1 Enabled (All data in this group will be written
to registers ADDR, ADDR+4, … ADDR+4 *
(LEN-1) sequentially
30 Wait
0 Don’t Wait (send data to the Graphics Engine
as long as it can receive it)
1 Wait (until the GE is idle, then send data)
29-8 Register Address of the First Data (ADDR)
15-0 Number of DWORDs of Data in this Group (LEN)