Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -60- Graphics Accelerator PCI Bus Master Registers
Technologies, Inc.
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Port 2310 – Graphics Bus Master System Start Addr ...RW
31-0 System Start Address
If scatter / gather is enabled, bits 31:12 point to the
physical region translation table (the page starting
address must be aligned on 4KB address boundaries)
and bits 11:0 are the offset within a page.
Physical Region Descriptor Table
While system memory is allocated in a non-contiguous space,
software needs to provide a physical region description table
in system memory and pass the table's starting address to
hardware.
The table size must less than or equal to 4K bytes and the table
cannot cross the 4K boundary.
Figure 5. Physical Region Descriptor Table Format
BYTE3 | BYTE2 | BYTE1 | BYTE0
Page 0 physical address |EOT
Page 1 physical address |EOT
......
Page n physical address |EOT
EOT = End of Table
Each table entry is 4 bytes in length. Hardware assumes that
the physical page is always 4K. Bits 31:2 indicate the
physical page starting address. Bit 0 of the first byte indicates
the end of the table. Bus Master operation terminates when
the last descriptor has been retired.
Port 2314 – Graphics Bus Master Height........................RW
15-10 Reserved ......................................... always reads 0
9-0 Source Data Height
Port 2316 – Graphics Bus Master Width.........................RW
15-12 Reserved ......................................... always reads 0
11-0 Source Data Width (in bytes)
Port 2318 – Graphics Bus Master FB Start Addr/Pitch RW
31-22 Frame Buffer Line Offset (FB pitch) in quadwords
21-20 Reserved ......................................... always reads 0
19-0 Frame Buffer Start Address (quadword aligned)
Port 231C – Graphics Bus Master System Pitch ............RW
15-12 Reserved ......................................... always reads 0
11-0 System Row Byte Offset (pitch) in bytes
Port 2320 – Graphics Bus Master Clear Data.................RW
31-0 Clear Data Value
Used as the “clear” value for “block transfer with
clear”
Figure 6. PCI Bus Master Address Translation
31 ................ 12 11 ...... 0
Physical Region
Description Table
Physical Memory
System Start Address
Register at 2210