Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -59- Graphics Accelerator PCI Bus Master Registers
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Graphics Accelerator PCI Bus Master Registers
The PLE133 PCI Bus Master controller supports both
read/write and scatter/gather. Software can take advantage of
this feature to transfer data between system memory and the
frame buffer. After software sets the proper registers and
commands, the PCI master begins to transfer data
automatically between system memory and the frame buffer.
This allows the CPU to do other jobs at the same time, thus
increasing performance.
Software should use the PCI Bus Master functionality to
transfer big chunks of data such as video capture data for
video conferencing applications or texture data for 3-D
applications. For small chunks of data, direct CPU access to
the Frame Buffer is the preferred method.
The software sequence used to control bus master operation is
as follows: Software first sets registers such as the system
memory starting address, page table starting address / height /
width, and frame buffer starting address and line offset.
Software finally sets the bus master control register where
either bit 1 (for reads) or bit 2 (for writes) is set as the
command bit. After the command bit is set, the hardware will
begin to transfer data automatically based on the parameters
specified. After the transfer is finished, the hardware will
issue an interrupt. Software can then poll the status bit to get
the transfer status. The hardware will clear the command bit
after the transfer is finished. Software cannot issue new
commands until the previous command is completed.
All Registers are memory mapped. The memory address base
is defined in PCI configuration register “Memory Base 1”
(offset 17h-14h).
Port 2204 – Graphics Bus Master Status......................... RO
31-3 Reserved .........................................always reads 0
2 Bus Master Interrupt Status
1 End of Transfer
0 Still processing....................................... default
1 End of Transfer (Idle)
0 Bus Master Error Status
0 Normal ................................................... default
1 Error Detected
This error is ususlly detected because the total page
table size is less than the size defined in the
“Graphics Bus Master Height” register at index
2314h.
Port 2300 – Graphics Bus Master Control ......................RW
31-16 Reserved ......................................... always reads 0
15 PCI Master Read Data to GE SRCQ
0 Disable ....................................................default
1 Enable
14-11 Bytes in DW to be Cleared
When enabling block transfer with clear, one bits
define which byte(s) in the DW will be cleared
10 Enable Bit with Clear
0 Disable ....................................................default
1 Enable
9 Invert C / Z Position
0 Hardware assumes C is located in bits 15:0
and Z in bits 31:16..................................default
1 Hardware assumes C is located in bits 31:16
and Z in bits 15:0
8 Enable Z Stripping
0 Disable ....................................................default
1 Enable
7-5 Reserved .........................................always reads 0
4 Bus Master Interrupt
0 Disable ....................................................default
1 Enable
3 Master Latency
0 Disable ....................................................default
1 Enable
2 Write Command ........................................ default =0
Writing this bit to 1 will trigger the hardware to begin
a write operation. After finishing the operation,
hardware will automatically clear this bit.
1 Read Command ........................................ default =0
Writing this bit to 1 will trigger the hardware to begin
a read operation. After finishing the operation,
hardware will automatically clear this bit.
0 Scatter / Gather
0 Disable ....................................................default
1 Enable