Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -57- Device 0 Bus 1 Header Registers - Graphics Accelerator
Technologies, Inc.
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Offset 8 - Revision ID......................................................... RO
8-0 VT8601A Graphics Controller Revision Code
Offset 9 - Programming Interface .................................... RO
7-0 Interface Identifier............................always reads 00
Offset A - Sub Class Code.................................................. RO
7-0 Sub Class Code..................................always reads 00
Offset B - Base Class Code ................................................ RO
7-0 Base Class Code
Reads 03 to indicate Graphics Controller
Offset 13-10 - Graphics Memory Base 0 ..........................RW
31-0 Graphics Memory Base 0......... default = E000 0000
Defines an 8MB space for display memory
Offset 17-14 - Graphics Memory Base 1 ..........................RW
31-0 Graphics Memory Base 0......... default = E080 0000
Defines a 128KB space for memory mapped I/O
Offset 1B-18 - Graphics Memory Base 2 .........................RW
31-0 Graphics Memory Base 0......... default = E040 0000
Defines an 8MB space for off-screen video overlay
Offset 2D-2C – Subsystem Vendor ID..............................RW
15-0 Subsystem Vendor ID.............................default = 00
Offset 2F-2E - Subsystem ID.............................................RW
15-0 Subsystem ID...........................................default = 00
Offset 33-30 –Graphics ROM Base ..................................RW
31-0 Graphics ROM Base..................default = 0000 0001
Offset 3C – Interrupt Line ................................................RW
7-0 Interrupt Line .......................................default = 0Bh
Offset 3D – Interrupt Pin ...................................................RO
7-0 Interrupt Pin ....................always reads 01h (INTA#)
Interrupts
There are several interrupt sources and their corresponding
controls in the PLE133 as shown in the following table:
Table 7. Interrupt Sources and Controls
Source Mask Clear Status
Capture
3
CR9B[7] CR9B[6]
1
CR9B[4]
Capture VSYNC
2
Capture Even Field
2
Capture Odd Field
2
Capture Blank
2
GE
4
2122[7] 2122[7] 2120[4]
VGA
5
CR11[5] CR11[4]
1) Write 0 to clear.
2) Selected by CR9E[7:6]
3) Video capture logic can generate an interrupt which is
selected from one of four sources determined by
CR9E.[7:6]. This interrupt is enabled by CR9B[7]. To
clear this bit write 0 to CR9B[6]. Whether an interrupt is
generated can be determined from CR9B[4].
4) The GE interrupt is similar to the capture interrupt.
5) The VGA interrupt is similar to the capture interrupt
except that there is no status bit.