Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -56- Device 0 Bus 1 Header Registers - Graphics Accelerator
Technologies, Inc.
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Offset 5-4 - Command........................................................RW
15-10 Reserved .........................................always reads 0
9 Fast Back-to-Back Cycle Enable.........................RO
0 Fast back-to-back transactions only allowed to
the same agent
1 Fast back-to-back transactions allowed to
different agents
8 SERR# Enable.......................................................RO
0 SERR# driver disabled........................... default
1 SERR# driver enabled
(SERR# is used to report parity errors if bit-6 is set).
7 Address / Data Stepping.......................................RO
0 Device never does stepping ................... default
1 Device always does stepping
6 Parity Error Response..........................................RO
0 Ignore parity errors & continue ............. default
1 Take normal action on detected parity errors
5 VGA Palette Snoop ..............................................RW
0 Treat palette accesses normally ............. default
1 Don’t respond to palette accesses on PCI bus
4 Memory Write and Invalidate Command..........RO
0 Bus masters must use Mem Write ......... default
1 Bus masters may generate Mem Write & Inval
3 Special Cycle Monitoring.....................................RO
0 Does not monitor special cycles ............ default
1 Monitors special cycles
2 Bus Master ..........................................................RW
0 Never behaves as a bus master .............. default
1 Can behave as a bus master
1 Memory Space......................................................RW
0 Does not respond to memory space
1 Responds to memory space.................... default
0 I/O Space ..........................................................RW
0 Does not respond to I/O space
1 Responds to I/O space ........................... default
Offset 7-6 - Status............................................................RWC
15 Detected Parity Error
0 No parity error detected..........................default
1 Error detected in either address or data phase.
This bit is set even if error response is disabled
(command register bit-6). ......write one to clear
14 Signaled System Error (SERR# Asserted)
.........................................always reads 0
13 Signaled Master Abort (Bus Master Only)
0 No abort received....................................default
1 Transaction aborted by the master ....................
.....................................write one to clear
12 Received Target Abort (Bus Master Only)
0 No abort received....................................default
1 Transaction aborted by the target ......................
........................................ write 1 to clear
11 Signaled Target Abort........................always reads 0
0 Target Abort never signaled
10-9 DEVSEL# Timing
00 Fast
01 Medium....................................always reads 01
10 Slow
11 Reserved
8 Data Parity Error Detected (Bus Master Only)
0 No data parity error detected .....always reads 0
1 Error detected in data phase
7 Fast Back-to-Back Capable
0 Not capable .............................................default
1 Capable
6 Reserved ......................................... always reads 0
5 66MHz Capable ..................................always reads 1
4 Supports New Capability list.............always reads 0
3-0 Reserved ......................................... always reads 0