Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -55- Device 0 Bus 1 Header Registers - Graphics Accelerator
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Device 0 Bus 1 Header Registers - Graphics Accelerator
The Apollo PLE133 2D / 3D Graphics Accelerator is fully
compliant with PCI bus interface protocol revision 2.2. The
controller implements slave functions of PCI to accept cycles
initiated by PCI masters targeted for its internal registers,
RAMDAC™, frame buffer, and/or BIOS. It will accept only
one data transaction for non-memory type transfers; however
burst read/write transfers for frame buffer accesses are also
implemented for performance enhancement. Bursting is
disabled when accessing memory mapped I/O. Data parity
will be generated for read cycles.
To support the PC AT architecture, palette snooping is
supported. There are two different palette snooping modes:
(1) snooping due to PCI retry, and (2) snooping due to master
abort. Both modes are supported. The video BIOS will
automatically determine the correct snooping mode in a PCI
based system during power up. The PLE133 follows the PCI
2.2 specification running at 33 MHz or lower system clock
frequencies. For packed pixel modes, if the first data TRDY is
not generated within 16 clocks, a retry will be issued. During
bursting, if successful data is not generated within 8 clocks, a
retry will also be issued.
The table below lists the commands implemented by the
PLE133 graphics controller PCI interface. Note that codes not
listed (0000 interrupt acknowledge, 0001 special cycle, 0100,
0101, 1000, 1001 reserved, and 1101 dual address cycle) are
not decoded and DEVSEL# is not generated. No action takes
place inside the chip for these codes.
Table 6. Supported PCI Command Codes
Command Code Command
0010 I/O Read
0011 I/O Write
0110 Memory Read
0111 Memory Write
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
(treated as simple memory read)
1110 Memory Read Line
(treated as simple memory read)
1111 Memory Write and Invalid
(treated as simple memory write)
The PCI configuration space is fully implemented. Due to the
second memory base register, all I/O registers can be memory
mapped; which allows more than one graphics controller to be
installed within a system by mapping memory and I/O to
different locations.
All configuration registers are located in PCI configuration
space and should be programmed using PCI configuration
mechanism 1 through CF8 / CFC with bus
number equal to
one
and function number and device number equal to zero.
There are three memory base registers. The first defines the
memory base location for the graphics frame buffer. The
second defines the memory base for the memory mapped I/O
locations. The third defines the memory base for the second
video aperture. With this second aperture, graphics data and
video data can be sent to the PLE133 simultaneously.
The PLE133 supports the PCI Bus Master mode which can
send captured video data directly to system memory for
processing. The registers to control the PCI Bus Master are
defined in following sections (they are all in PCI configuration
space).
Offset 1-0 - Vendor ID (1023h) ..........................................RO
15-0 ID Code .................................always reads 1023h
Offset 3-2 - Device ID (8500h)............................................RO
15-0 ID Code .................................always reads 8500h