Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -54- Device 1 Bus 0 PCI-to-AGP Bridge Registers
Technologies, Inc.
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Device 1 Bus 0 PCI-to-AGP Bridge Registers
AGP Bus Control
Device 1 Offset 40 - CPU-to-AGP Flow Control 1..........RW
7 CPU-AGP Post Write
0 Disable ................................................... default
1 Enable
6 CPU-AGP Dynamic Burst
0 Disable ................................................... default
1 Enable
5 CPU-AGP One Wait State Burst Write
0 Disable ................................................... default
1 Enable
4 AGP to DRAM Prefetch
0 Disable ................................................... default
1 Enable
3 AGP Master Allowed Before CPU-to-AGP Post
Write Buffer is Not Flushed
0 Disable ................................................... default
1 Enable
This option is always enabled for PCI
2 MDA Present on AGP
0 Forward MDA accesses to AGP............ default
1 Forward MDA accesses to PCI
Note: Forward despite IO / Memory Base / Limit
Note: MDA (Monochrome Display Adapter)
addresses are memory addresses B0000h-B7FFFh
and I/O addresses 3B4-3B5h, 3B8-3BAh, and 3BFh
(10-bit decode). 3BC-3BE are reserved for printers.
Note: If Rx3E bit-3 is 0, this bit is a don't care
(MDA accesses are forwarded to the PCI bus).
1 AGP Master Read Caching
0 Disable ................................................... default
1 Enable
0 AGP Delay Transaction
0 Disable ................................................... default
1 Enable
Table 5. VGA/MDA Memory/IO Redirection
3E[3]
VGA
Pres.
40[2]
MDA
Pres.
VGA
is
on
MDA
is
on
Axxxx,
B8xxx
Access
B0000
-B7FFF
Access
3Cx,
3Dx
I/O
3Bx
I/O
0 - PCI PCI PCI PCI PCI PCI
1 0 AGP AGP AGP AGP AGP AGP
1 1 AGP PCI AGP PCI AGP PCI
Device 1 Offset 41 - CPU-to-AGP Flow Control 2.......RWC
7 Retry Status
0 No retry occurred....................................default
1 Retry Occurred.........................write 1 to clear
6 Retry Timeout Action
0 No action taken except to record status........def
1 Flush buffer for write or return all 1s for read
5-4 Retry Count
00 Retry 2, backoff CPU .............................default
01 Retry 4, backoff CPU
10 Retry 16, backoff CPU
11 Retry 64, backoff CPU
3 Post Write Data on Abort
0 Flush entire post-write buffer on target-abort
or master abort ........................................default
1 Pop one data output on target-abort or master-
abort
2 CPU Backoff on AGP Read Retry Timeout
0 Disable ....................................................default
1 Enable
1-0 Reserved .........................................always reads 0
Device 1 Offset 42 - AGP Master Control .......................RW
7 Read Prefetch for Enhance Command
0 Always Perform Prefetch........................default
1 Prefetch only if Enhance Command
6 AGP Master One Wait State Write
0 Disable ....................................................default
1 Enable
5 AGP Master One Wait State Read
0 Disable ....................................................default
1 Enable
4 Extend AGP Internal Master for Efficient
Handling of Dummy Request Cycles
0 Disable ....................................................default
1 Enable
This bit is normally set to 1.
3 AGP Delay Transaction Timeout
0 Disable ....................................................default
1 Enable
2 Prefetch During Delay Transaction
0 Enable .....................................................default
1 Disable
1 Reserved .........................................always reads 0
0 Reserved (do not use) ............................... default = 0