Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -53- Device 1 Bus 0 Header Registers - PCI-to-AGP Bridge
Technologies, Inc.
Delivering Value
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Device 1 Offset 18 - Primary Bus Number ......................RW
7-0 Primary Bus Number ...............................default = 0
This register is read write, but internally the chip always uses
bus 0 as the primary.
Device 1 Offset 19 - Secondary Bus Number...................RW
7-0 Secondary Bus Number............................default = 0
Note: PCI#2 must use these bits to convert Type 1 to Type 0.
Device 1 Offset 1A - Subordinate Bus Number...............RW
7-0 Primary Bus Number ...............................default = 0
Note: PCI#2 must use these bits to decide if Type 1 to Type 1
command passing is allowed.
Device 1 Offset 1C - I/O Base............................................RW
7-4 I/O Base AD[15:12]...........................default = 1111b
3-0 I/O Addressing Capability.......................default = 0
Device 1 Offset 1D - I/O Limit ..........................................RW
7-4 I/O Limit AD[15:12] .................................default = 0
3-0 I/O Addressing Capability.......................default = 0
Device 1 Offset 1F-1E - Secondary Status ....................... RO
15-0 Reserved ...................................always reads 0000
Device 1 Offset 21-20 - Memory Base...............................RW
15-4 Memory Base AD[31:20]................. default = 0FFFh
3-0 Reserved .........................................always reads 0
Device 1 Offset 23-22 - Memory Limit (Inclusive)..........RW
15-4 Memory Limit AD[31:20] ........................default = 0
3-0 Reserved .........................................always reads 0
Device 1 Offset 25-24 - Prefetchable Memory Base........RW
15-4 Prefetchable Memory Base AD[31:20] def = 0FFFh
3-0 Reserved .........................................always reads 0
Device 1 Offset 27-26 - Prefetchable Memory Limit ......RW
15-4 Prefetchable Memory Limit AD[31:20]...................
...............................................default = 0
3-0 Reserved .........................................always reads 0
Device 1 Offset 3F-3E – PCI-to-PCI Bridge Control .....RW
15-4 Reserved .........................................always reads 0
3 VGA-Present on AGP
0 Forward VGA accesses to PCI Bus........default
1 Forward VGA accesses to AGP Bus
Note: VGA addresses are memory A0000-BFFFFh
and I/O addresses 3B0-3BBh, 3C0-3CFh and 3D0-
3DFh (10-bit decode). "Mono" text mode uses
B0000-B7FFFh and "Color" Text Mode uses B8000-
BFFFFh. Graphics modes use Axxxxh. Mono VGA
uses I/O addresses 3Bx-3Cxh and Color VGA uses
3Cx-3Dxh. If an MDA is present, a VGA will not
use the 3Bxh I/O addresses and B0000-B7FFFh
memory space; if not, the VGA will use those
addresses to emulate MDA modes.
2 Block / Forward ISA I/O Addresses
0 Forward all I/O accesses to the AGP bus if
they are in the range defined by the I/O Base
and I/O Limit registers (device 1 offset 1C-
1D)
......................................................default
1 Do not forward I/O accesses to the AGP bus
that are in the 100-3FFh address range even if
they are in the range defined by the I/O Base
and I/O Limit registers.
1-0 Reserved .........................................always reads 0