Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -52- Device 1 Bus 0 Header Registers - PCI-to-AGP Bridge
Technologies, Inc.
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Device 1 Bus 0 Header Registers - PCI-to-AGP Bridge
All registers are located in PCI configuration space. They
should be programmed using PCI configuration mechanism 1
through CF8 / CFC with bus
number and function number
equal to zero
and device number equal to one.
Device 1 Offset 1-0 - Vendor ID........................................ RO
15-0 ID Code (reads 1106h to identify VIA Technologies)
Device 1 Offset 3-2 - Device ID.......................................... RO
15-0 ID Code (reads 8601h to identify the VT8601A PCI-
to-PCI Bridge device)
Device 1 Offset 5-4 - Command ........................................RW
15-10 Reserved .........................................always reads 0
9 Fast Back-to-Back Cycle Enable.........................RO
0 Fast back-to-back transactions only allowed to
the same agent........................................ default
1 Fast back-to-back transactions allowed to
different agents
8 SERR# Enable.......................................................RO
0 SERR# driver disabled........................... default
1 SERR# driver enabled
(SERR# is used to report parity errors if bit-6 is set).
7 Address / Data Stepping.......................................RO
0 Device never does stepping ................... default
1 Device always does stepping
6 Parity Error Response.........................................RW
0 Ignore parity errors & continue ............. default
1 Take normal action on detected parity errors
5 VGA Palette Snoop ...............................................RO
0 Treat palette accesses normally ............. default
1 Don’t respond to palette writes on PCI bus
(10-bit decode of I/O addresses 3C6-3C9 hex)
4 Memory Write and Invalidate Command..........RO
0 Bus masters must use Mem Write ......... default
1 Bus masters may generate Mem Write & Inval
3 Special Cycle Monitoring.....................................RO
0 Does not monitor special cycles ............ default
1 Monitors special cycles
2 Bus Master ..........................................................RW
0 Never behaves as a bus master
1 Enable to operate as a bus master on the
primary interface on behalf of a master on the
secondary interface ............................... default
1 Memory Space......................................................RW
0 Does not respond to memory space
1 Enable memory space access ................ default
0 I/O Space ..........................................................RW
0 Does not respond to I/O space
1 Enable I/O space access ........................ default
Device 1 Offset 7-6 - Status (Primary Bus)...................RWC
15 Detected Parity Error.........................always reads 0
14 Signaled System Error (SERR#).......always reads 0
13 Signaled Master Abort
0 No abort received....................................default
1 Transaction aborted by the master with
Master-Abort (except Special Cycles)...............
........................................ write 1 to clear
12 Received Target Abort
0 No abort received....................................default
1 Transaction aborted by the target with Target-
Abort ........................................ write 1 to clear
11 Signaled Target Abort........................always reads 0
10-9 DEVSEL# Timing
00 Fast
01 Medium....................................always reads 01
10 Slow
11 Reserved
8 Data Parity Error Detected ...............always reads 0
7 Fast Back-to-Back Capable...............always reads 0
6 User Definable Features.....................always reads 0
5 66MHz Capable ..................................always reads 1
4 Supports New Capability list.............always reads 0
3-0 Reserved ......................................... always reads 0
Device 1 Offset 8 - Revision ID ..........................................RO
7-0 VT8601A Chip Revision Code (00=First Silicon)
Device 1 Offset 9 - Programming Interface......................RO
This register is defined in different ways for each Base/Sub-
Class Code value and is undefined for this type of device.
7-0 Interface Identifier ...........................always reads 00
Device 1 Offset A - Sub Class Code...................................RO
7-0 Sub Class Code. reads 04 to indicate PCI-PCI Bridge
Device 1 Offset B - Base Class Code..................................RO
7-0 Base Class Code ..reads 06 to indicate Bridge Device
Device 1 Offset D - Latency Timer....................................RO
7-0 Reserved ......................................... always reads 0
Device 1 Offset E - Header Type .......................................RO
7-0 Header Type Code.......... reads 01: PCI-PCI Bridge
Device 1 Offset F - Built In Self Test (BIST)....................RO
7 BIST Supported...... reads 0: no supported functions
6 Start Test ...........write 1 to start but writes ignored
5-4 Reserved .........................................always reads 0
3-0 Response Code ......... 0 = test completed successfully