Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -51- Device 0 Bus 0 Host Bridge Registers
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
Device 0 Offset F7-F0 – BIOS Scratch Register..............RW
7-0 No Hardware Function
Device 0 Offset F8 – DRAM Arbitration Timer 1 ..........RW
7-4 AGP Timer (units of 4 DRAM Clocks)
3-0 Host Timer (units of 4 DRAM Clocks)
Device 0 Offset F9 – DRAM Arbitration Timer 2 ..........RW
7-4 VGA High Priority Timer (units of 16 DRAM
Clocks)
3-0 VGA Timer (units of 16 DRAM Clocks)
Device 0 Offset FA – CPU Direct Access Frame Buffer
Base Address A[28:21].......................................................RW
7-0 A[28:21]
Device 0 Offset FB – Frame Buffer Control....................RW
7 VGA Enable
0 Disable ................................................... default
1 Enable
6 VGA Reset ..................................(Write 1 to Reset)
5-4 Frame Buffer Size
00 None ..................................................... default
01 2M
10 4M
11 8M
3 CPU Direct Access Frame Buffer
0 Disable ................................................... default
1 Enable
2-0 CPU Direct Access Frame Buffer Base Address
<31:29>
Device 0 Offset FC – Back Door Control 1......................RW
7-2 Reserved .........................................always reads 0
1 Back-Door Max # of AGP Requests Allowed
0 Read RXA7 will return 7........................default
1 Read RxXA7 will have number programmed
at RxFD
0 Back-Door Device ID Enable
0 Use Rx3-2’s value for Rx3-2 read..........default
1 Use the value in RxFE-FF
Device 0 Offset FD – Back Door Control 2......................RW
7-3 Reserved
2-0 Back-Door Max # of AGP Requests the Device can
Handle
000 1-Request ................................................default
001 2-Requests
… …
111 8-Requests
Device 0 Offset FF-FE – Back Door Device ID ...............RW
15-0 Back-Door Device ID................................ default = 0