Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -50- Device 0 Bus 0 Host Bridge Registers
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
AGP Control
Device 0 Offset A3-A0 - AGP Capability Identifier........ RO
31-24 Reserved .......................................always reads 00
23-20 Major Specification Revision ......always reads 0001
Major revision # of AGP spec device conforms to
19-16 Minor Specification Revision ......always reads 0000
Minor revision # of AGP spec device conforms to
15-8 Pointer to Next Item ....... always reads 00 (last item)
7-0 AGP ID ..(always reads 02 to indicate it is AGP)
Device 0 Offset A7-A4 - AGP Status ................................ RO
31-24 Maximum AGP Requests.................always reads 07
Max # of AGP requests the device can manage (8)
23-10 Reserved ....................................... always reads 0s
9 Supports SideBand Addressing.........always reads 1
8-2 Reserved ....................................... always reads 0s
1 2X Rate Supported
Value returned can be programmed by writing to
RxAC[3] .........................................always reads 1
0 1X Rate Supported..............................always reads 1
Device 0 Offset AB-A8 - AGP Command ........................RW
31-24 Request Depth (reserved for target) .. always reads 0s
23-10 Reserved ....................................... always reads 0s
9 SideBand Addressing Enable
0 Disable ................................................... default
1 Enable
8 AGP Enable
0 Disable ................................................... default
1 Enable
7-2 Reserved ....................................... always reads 0s
1 2X Mode Enable
0 Disable ................................................... default
1 Enable
0 1X Mode Enable
0 Disable ................................................... default
1 Enable
Device 0 Offset AC - AGP Control...................................RW
7 Reserved ....................................... always reads 0s
6 AGP Read Synchronization
0 Disable ....................................................default
1 Enable (the CPU to AGP cycle will be delayed
if the CMFIFO contains a GART access)
5 AGP Read Snoop CMFIFO
0 Disable ....................................................default
1 Enable (AGP read address will snoop the
CMFIFO; if hit, AGP read will be started after
the write is retired)
4 AGP Master Request has Higher Priority if AGP
Controller is Parking at AGP Master
0 Disable ....................................................default
1 Enable
3 2X Rate Supported (read also at RxA4[1])
0 Not supported..........................................default
1 Supported
2 LPR In-Order Access (Force Fence)
0 Fence/Flush functions not guaranteed. AGP
read requests (low/normal priority and high
priority) may be executed before previously
issued write requests...............................default
1 Force all requests to be executed in order
(automatically enables Fence/Flush functions).
Low (i.e., normal) priority AGP read requests
will never be executed before previously
issued writes. High priority AGP read
requests may still be executed prior to
previously issued write requests as required.
1 AGP Arbitration Parking
0 Disable ....................................................default
1 Enable (GGNT# remains asserted until either
GREQ# de-asserts or data phase ready)
0 2T AGP to DRAM Request Generation
0 Disable ....................................................default
1 Enable
Device 0 Offset AD – AGP Latency Register ..................RW
7-4 Reserved ....................................... always reads 0s
3-0 AGP Latency Timer(units of 16 GCLKs)
0000 Free Run..................................................default