Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -47- Device 0 Bus 0 Host Bridge Registers
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
Device 0 Offset 78 - PMU Control 1 .................................RW
7 I/O Port 22 Access
0 CPU access to I/O address 22h is passed on to
the PCI bus............................................. default
1 CPU access to I/O address 22h is processed
internally
6 Suspend Refresh Type
0 CBR Refresh .......................................... default
1 Self Refresh
5 Reserved .........................................always reads 0
4 Dynamic Clock Control
0 Normal (clock is always running).......... default
1 Clock to various internal functional blocks is
disabled when those blocks are not being used
3 Reserved .........................................always reads 0
2 AGPSTP# Control
0 Disable ................................................... default
1 Enable
1 Reserved .........................................always reads 0
0 Memory Clock Enable (CKE) Function
0 CKE Disable (pins used as MECC[2-0])..... def
1 CKE Enable (pins used for CKE[2-0]#)
Device 0 Offset 79 – PMU Control 2.................................RW
7 CPU Interface Controller Dynamic Clock
Stopping
0 Disable ................................................... default
1 Enable
6 DRAM Controller Dynamic Clock Stopping
0 Disable ................................................... default
1 Enable
5 AGP Controller Dynamic Clock Stopping
0 Disable ................................................... default
1 Enable
4 PCI Interface Controller Dynamic Clock Stopping
0 Disable ................................................... default
1 Enable
3 Pseudo Power Good
0 Disable ................................................... default
1 Enable
2 South Bridge has High Priority
0 Disable ................................................... default
1 Enable
1-0 Reserved .........................................always reads 0
Device 0 Offset 7A – Miscellaneous Control ...................RW
7 No Time-Out Arbitration for Consecutive Frame
Accesses
0 Enable .....................................................default
1 Disable
6-4 Reserved .........................................always reads 0
3 Background PCI-to-PCI Write Cycle Mode
0 Enable .....................................................default
1 Disable
2-1 Reserved .........................................always reads 0
0 South Bridge PCI Master Force Timeout When
PCI Master Occupancy Timer Is Up
0 Disable ....................................................default
1 Enable
Device 0 Offset 7E – PLL Test Mode...............................RW
7-6 Reserved (status)................................................... RO
5-0 Reserved (do not use) ................................. default=0
Device 0 Offset 7F – PLL Test Mode ...............................RW
7-0 Reserved (do not use) ................................. default=0