Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -44- Device 0 Bus 0 Host Bridge Registers
Technologies, Inc.
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PCI Bus Control
These registers are normally programmed once at system
initialization time.
Device 0 Offset 70 - PCI Buffer Control ..........................RW
7 CPU to PCI Post-Write
0 Disable ................................................... default
1 Enable
6 PCI Master to DRAM Post-Write
0 Disable ................................................... default
1 Enable
5 Reserved
4 PCI Master to DRAM Prefetch Disable
0 Enable..................................................... default
1 Disable
3 CPU-to-PCI Buffer Available Cycle Reduction
0 Normal operation ................................... default
1 Reduce 1 cycle when the CPU-to-PCI buffer
becomes available after being full (PCI and
AGP buses)
2 PCI Master Read Caching
0 Disable ................................................... default
1 Enable
1 Delay Transaction
0 Disable ................................................... default
1 Enable
0 Slave Device Stopped Idle Cycle Reduction
0 Normal Operation .................................. default
1 Reduce 1 PCI idle cycle when stopped by a
slave device (PCI and AGP buses)
Device 0 Offset 71 - CPU to PCI Flow Control 1............RW
7 Dynamic Burst
0 Disable ....................................................default
1 Enable (see note under bit-3 below)
6 Byte Merge
0 Disable ....................................................default
1 Enable
5 Reserved (do not program)........................ default = 0
4 PCI I/O Cycle Post Write
0 Disable ....................................................default
1 Enable
3 PCI Burst
0 Disable ....................................................default
1 Enable (bit7=1 will override this option)
bit-7
bit-3 Operation
0 0 Every write goes into the write buffer and no
PCI burst operations occur.
0 1 If the write transaction is a burst transaction,
the information goes into the write buffer and
burst transfers are later performed on the PCI
bus. If the transaction is not a burst, PCI write
occurs immediately (after a write buffer flush).
1 x Every write transaction goes to the write
buffer; burstable transactions will then burst
on the PCI bus and non-burstable won’t. This
is the normal setting.
2 PCI Fast Back-to-Back Write
0 Disable ....................................................default
1 Enable
1 Quick Frame Generation
0 Disable ....................................................default
1 Enable
0 1 Wait State PCI Cycles
0 Disable ....................................................default
1 Enable