Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -42- Device 0 Bus 0 Host Bridge Registers
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
Device 0 Offset 69 – DRAM Clock Select (00h)...............RW
7-6 DRAM Operating Frequency Select..................RW
Rx68[1-0]
Rx69[7-6] Rx68[4] CPU/DRAM/VGA
00 00 x 66/66/66 (default)
00 01 x 66/100/100
01 00 x 100/100/100
01 10 x 100/66/66
01 01 1 100/133/133
10 00 1 133/133/133
10 10 x 133/100/100
All other combinations are reserved. The internal
graphics controller runs synchronous to the DRAM
and at the same frequency (if the DRAM controller
frequency is set to 133, Rx68[4] must also be set to
1).
5 256M bit DRAM Support
0 Disable ................................................... default
1 Enable (DCLKRD becomes output)
4 DRAM Controller Command Register Output
0 Disable ................................................... default
1 Enable
3 Fast DRAM Precharge for Different Bank
0 Disable ................................................... default
1 Enable
2 DRAM 4K Pages (for 64Mbit DRAM)
0 Disable ................................................... default
1 Enable
1 Reserved (Do Not Program) ....................default = 0
0 Reserved .........................................always reads 0
Device 0 Offset 6A - Refresh Counter..............................RW
7-0 Refresh Counter (in units of 16 MCLKs)
00 DRAM Refresh Disabled........................default
01 32 MCLKs
02 48 MCLKs
03 64 MCLKs
04 80 MCLKs
05 96 MCLKs
… …
The programmed value is the desired number of 16-
MCLK units minus one.
Device 0 Offset 6B - DRAM Arbitration Control (01h).RW
7-6 Arbitration Parking Policy
00 Park at last bus owner.............................default
01 Park at CPU side
10 Park at AGP side
11 Reserved
5 Fast Read to Write Turnaround
0 Disable ....................................................default
1 Enable
4 Reserved .........................................always reads 0
3 MD Bus Second Level Strength Control
0 Normal slew rate control ........................default
1 More slew rate control
2 CAS Second Level Strength Control
0 Normal slew rate control ........................default
1 More slew rate control
1 Reserved (Do Not Program) .................... default = 0
0 Multi-Page Open
0 Disable (page registers marked invalid and no
page register update which causes non page-
mode operation)
1 Enable .....................................................default