Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -41- Device 0 Bus 0 Host Bridge Registers
Technologies, Inc.
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Device 0 Offset 64 - DRAM Timing for Banks 0,1..........RW
Device 0 Offset 65 - DRAM Timing for Banks 2,3..........RW
Device 0 Offset 66 - DRAM Timing for Banks 4,5..........RW
Settings for Registers 64-66
7 Precharge Command to Active Command Period
0 T
RP = 2T
1 T
RP = 3T ................................................ default
6 Active Command to Precharge Command Period
0 T
RAS = 5T
1 T
RAS = 6T .............................................. default
5-4 CAS Latency
00 1T
01 2T
10 3T ..................................................... default
11 Reserved
3 Reserved (Do Not Program) ....................default = 0
2 ACTIVE Command to CMD Command Period
0 2T
1 3T ..................................................... default
1-0 Bank Interleave
00 No Interleave.......................................... default
01 2-way
10 4-way
11 Reserved
Device 0 Offset 68 - DRAM Control.................................RW
7 Reserved (Do Not Program) ................... default = 0
6 Bank Page Control
0 Allow only pages of the same bank active ...def
1 Allow pages of different banks to be active
5 Reserved (Do Not Program) ................... default = 0
4 Internal Graphics Controller Frequency
0 66 / 100 MHz ..........................................default
1 133 MHz
This bit must be set to 1 if the DRAM frequency is
133 MHz. If the DRAM frequency is set to 100 or 66
MHz this bit it ignored. (see also table under
Rx69[7-6]).
3 Reserved (Do Not Program) .................... default = 0
2 Burst Refresh
0 Disable ....................................................default
1 Enable (burst 4 times)
1-0 System Frequency Divider...................................RO
00 CPU / PCI Frequency Ratio = 2x (66 MHz)
01 CPU / PCI Frequency Ratio = 3x (100 MHz)
10 -reserved-
11 CPU / PCI Frequency Ratio = 4x (133 MHz)
These bits are latched from MA[14, 12] at the rising
edge of RESET#. Without external strapping
resistors, the default setting of these bits is 00 (66
MHz).