Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -40- Device 0 Bus 0 Host Bridge Registers
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
Device 0 Offset 61 - Shadow RAM Control 1..................RW
7-6 CC000h-CFFFFh
00 Read/write disable.................................. default
01 Write enable
10 Read enable
11 Read/write enable
5-4 C8000h-CBFFFh
00 Read/write disable.................................. default
01 Write enable
10 Read enable
11 Read/write enable
3-2 C4000h-C7FFFh
00 Read/write disable.................................. default
01 Write enable
10 Read enable
11 Read/write enable
1-0 C0000h-C3FFFh
00 Read/write disable.................................. default
01 Write enable
10 Read enable
11 Read/write enable
Device 0 Offset 62 - Shadow RAM Control 2..................RW
7-6 DC000h-DFFFFh
00 Read/write disable.................................. default
01 Write enable
10 Read enable
11 Read/write enable
5-4 D8000h-DBFFFh
00 Read/write disable.................................. default
01 Write enable
10 Read enable
11 Read/write enable
3-2 D4000h-D7FFFh
00 Read/write disable.................................. default
01 Write enable
10 Read enable
11 Read/write enable
1-0 D0000h-D3FFFh
00 Read/write disable.................................. default
01 Write enable
10 Read enable
11 Read/write enable
Device 0 Offset 63 - Shadow RAM Control 3..................RW
7-6 E0000h-EFFFFh
00 Read/write disable ..................................default
01 Write enable
10 Read enable
11 Read/write enable
5-4 F0000h-FFFFFh
00 Read/write disable ..................................default
01 Write enable
10 Read enable
11 Read/write enable
3-2 Memory Hole
00 None ......................................................default
01 512K-640K
10 15M-16M (1M)
11 14M-16M (2M)
1-0 SMI Mapping Control
00 Disable SMI Address Redirection..........default
01 Allow access to DRAM Axxxx-Bxxxx for
both normal and SMI cycles
10 Reserved
11 Allow SMI Axxxx-Bxxxx DRAM access
Note: The A0000-BFFFF address range is reserved
for use by VGA controllers for system access to the
VGA frame buffer. Since frame buffer accesses are
normally directed to the system VGA controller (with
its separate memory subsystem), system DRAM
locations in the A0000-BFFFF range would normally
be unused. Setting the above bits appropriately
allows this block of system memory to be used by
directing Axxxx-Bxxxx accesses to corresponding
memory addresses in system DRAM instead of
directing those accesses to the PCI bus for VGA
frame buffer access.