Product specifications
VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -39- Device 0 Bus 0 Host Bridge Registers
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
DRAM Control
These registers are normally set at system initialization time
and not accessed after that during normal system operation.
Some of these registers, however, may need to be programmed
using specific sequences during power-up initialization to
properly detect the type and size of installed memory (refer to
the VIA Technologies VT8601A BIOS porting guide for
details).
Table 3. System Memory Map
Space Start Size Address Range Comment
DOS 0 640K 00000000-0009FFFF Cacheable
VGA 640K 128K 000A0000-000BFFFF Used for SMM
BIOS 768K 16K 000C0000-000C3FFF Shadow Ctrl 1
BIOS 784K 16K 000C4000-000C7FFF Shadow Ctrl 1
BIOS 800K 16K 000C8000-000CBFFF Shadow Ctrl 1
BIOS 816K 16K 000CC000-000CFFFF Shadow Ctrl 1
BIOS 832K 16K 000D0000-000D3FFF Shadow Ctrl 2
BIOS 848K 16K 000D4000-000D7FFF Shadow Ctrl 2
BIOS 864K 16K 000D8000-000DBFFF Shadow Ctrl 2
BIOS 880K 16K 000DC000-000DFFFF Shadow Ctrl 2
BIOS 896K 64K 000E0000-000EFFFF Shadow Ctrl 3
BIOS 960K 64K 000F0000-000FFFFF Shadow Ctrl 3
Sys 1MB — 00100000-DRAM Top Can have hole
Bus D Top DRAM Top-FFFEFFFF
Init 4G-64K 64K FFFEFFFF-FFFFFFFF 000Fxxxx alias
Device 0 Offset 59-58 - DRAM MA Map Type ...............RW
15-13 Bank 5/4 MA Map Type
0xx 16Mb SDRAM....................................... default
100 64/128Mb SDRAM (x4, x8, x16, 4-bank x32)
101 Reserved (Do Not Program)
110 Reserved (Do Not Program)
111 Reserved (Do Not Program)
12 Reserved (Do Not Program) ......................default=0
11-8 Reserved .........................................always reads 0
7-5 Bank 1/0 MA Map Type (see above)
4 Reserved (Do Not Program) ......................default=0
3-1 Bank 3/2 MA Map Type (see above)
0 Reserved (Do Not Program) ......................default=0
Device 0 Offset 5A-5F – DRAM Row Ending Address:
All of the registers in this group default to 01h:
Offset 5A – Bank 0 Ending (HA[30:23]).....................RW
Offset 5B – Bank 1 Ending (HA[30:23]).....................RW
Offset 5C – Bank 2 Ending (HA[30:23]).....................RW
Offset 5D – Bank 3 Ending (HA[30:23]).....................RW
Offset 5E – Bank 4 Ending (HA[30:23]).....................RW
Offset 5F – Bank 5 Ending (HA[30:23]) .....................RW
Note: BIOS is required to fill the ending address registers
for all banks even if no memory is populated. The
endings have to be in incremental order.
Device 0 Offset 60 – DRAM Type.....................................RW
7-6 Reserved .........................................always reads 0
5-4 DRAM Type for Bank 5/4
00 Reserved..................................................default
01 Reserved
10 Reserved
11 SDRAM
3-2 DRAM Type for Bank 3/2.......................... default=0
1-0 DRAM Type for Bank 1/0.......................... default=0
Table 4. Memory Address Mapping Table
MA: 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16Mb (0xx)
11
11
22
PC
21
24
20
23
19
10
18
9
17
8
16
7
15
6
14
5
13
4
12
3
Row Bits
Col Bits
64Mb (100)
2/4 bank
x4, x8, x16;
4-bank x32
24
24
13
13
12
12
22
PC
21
26
20
25
19
10
18
9
17
8
16
7
15
6
14
5
11
4
23
3
x4: 10 col
x8: 9 col
x16: 8 col
x32: 8 col
"PC" = "Precharge Control" (refer to SDRAM specifications)
16Mb 11x10, 11x9, and 11x8 configurations supported
64Mb x4: 12x10 4bank, 13x10 2bank
x8: 12x9 4bank, 13x9 2bank
x16: 12x8 4bank, 13x8 2bank
x32: 11x8 4bank
128Mb same as 64Mb