Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -37- Device 0 Bus 0 Host Bridge Registers
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
Device 0 Offset 52 – Dynamic Defer Timer (10h) ...........RW
7 GTL I/O Buffer Pullup...........default = MA13 Strap
0 Disable
1 Enable
The default value of this bit is determined by a strap
on the MA13 pin during reset.
6 RAW Write Retire After 2 Writes
0 Disable ................................................... default
1 Enable
5 Reserved .........................................always reads 0
4-0 Snoop Stall Count
00 Disable dynamic defer
01-1F Snoop stall count .........................default = 10h
Device 0 Offset 53 – Miscellaneous (00h).........................RW
7 HREQ Function
0 Disable ....................................................default
1 Enable
6 DRAM Frequency Higher Than CPU FSB
0 Disable ....................................................default
1 Enable
Setting this bit enables the DRAM subsystem to run at
a higher frequency than the CPU FSB frequency.
When setting this bit, register bit Rx69[6] must also be
set and only SDRAM memory type DIMM modules
may be installed. An EDO / SDRAM mix in the
DRAM subsystem is not supported in this case.
5 AGP/PCI-to-CPU Master / CPU-to-PCI Slave
Concurrency
0 Disable ....................................................default
1 Enable
4 HPRI Function
0 Disable ....................................................default
1 Enable
3 P6Lock Function
0 Disable ....................................................default
1 Enable
2 P6Lock
0 Disable ....................................................default
1 Enable
1-0 Reserved ......................................... always reads 0