Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -34- Device 0 Bus 0 Header Registers - Host Bridge
Technologies, Inc.
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Register Descriptions
Device 0 Bus 0 Header Registers - Host Bridge
All registers are located in PCI configuration space. They
should be programmed using PCI configuration mechanism 1
through CF8 / CFC with bus
number, function number, and
device number
equal to zero.
Device 0 Offset 1-0 - Vendor ID........................................ RO
15-0 ID Code (reads 1106h to identify VIA Technologies)
Device 0 Offset 3-2 - Device ID.......................................... RO
15-0 ID Code (reads 0601h to identify the VT8601A)
Device 0 Offset 5-4 - Command ........................................RW
15-10 Reserved .........................................always reads 0
9 Fast Back-to-Back Cycle Enable.........................RO
0 Fast back-to-back transactions only allowed to
the same agent........................................ default
1 Fast back-to-back transactions allowed to
different agents
8 SERR# Enable.......................................................RO
0 SERR# driver disabled........................... default
1 SERR# driver enabled
(SERR# is used to report parity errors if bit-6 is set).
7 Address / Data Stepping.......................................RO
0 Device never does stepping ................... default
1 Device always does stepping
6 Parity Error Response.........................................RW
0 Ignore parity errors & continue ............. default
1 Take normal action on detected parity errors
5 VGA Palette Snoop ...............................................RO
0 Treat palette accesses normally ............. default
1 Don’t respond to palette accesses on PCI bus
4 Memory Write and Invalidate Command..........RO
0 Bus masters must use Mem Write ......... default
1 Bus masters may generate Mem Write & Inval
3 Special Cycle Monitoring.....................................RO
0 Does not monitor special cycles ............ default
1 Monitors special cycles
2 Bus Master ...........................................................RO
0 Never behaves as a bus master
1 Can behave as a bus master ................... default
1 Memory Space.......................................................RO
0 Does not respond to memory space
1 Responds to memory space.................... default
0 I/O Space ...........................................................RO
0 Does not respond to I/O space .............. default
1 Responds to I/O space
Device 0 Offset 7-6 - Status ............................................RWC
15 Detected Parity Error
0 No parity error detected..........................default
1 Error detected in either address or data phase.
This bit is set even if error response is disabled
(command register bit-6). ......write one to clear
14 Signaled System Error (SERR# Asserted)
.........................................always reads 0
13 Signaled Master Abort
0 No abort received....................................default
1 Transaction aborted by the master ....................
.....................................write one to clear
12 Received Target Abort
0 No abort received....................................default
1 Transaction aborted by the target ......................
........................................ write 1 to clear
11 Signaled Target Abort........................always reads 0
0 Target Abort never signaled
10-9 DEVSEL# Timing
00 Fast
01 Medium....................................always reads 01
10 Slow
11 Reserved
8 Data Parity Error Detected
0 No data parity error detected ..................default
1 Error detected in data phase. Set only if error
response enabled via command bit-6 = 1 and
VT8601A was initiator of the operation in
which the error occurred........write one to clear
7 Fast Back-to-Back Capable...............always reads 1
6 Reserved ......................................... always reads 0
5 66MHz Capable ..................................always reads 0
4 Supports New Capability list.............always reads 1
3-0 Reserved ......................................... always reads 0
Device 0 Offset 8 - Revision ID ..........................................RO
7-0 VT8601A Chip Revision Code
Device 0 Offset 9 - Programming Interface......................RO
7-0 Interface Identifier ...........................always reads 00
Device 0 Offset A - Sub Class Code...................................RO
7-0 Sub Class Code........reads 00 to indicate Host Bridge
Device 0 Offset B - Base Class Code..................................RO
7-0 Base Class Code ..reads 06 to indicate Bridge Device
Device 0 Offset D - Latency Timer...................................RW
Specifies the latency timer value in PCI bus clocks.
7-3 Guaranteed Time Slice for CPU ............... default=0
2-0 Reserved (fixed granularity of 8 clks)...always read 0
Bits 2-1 are writeable but read 0 for PCI specification
compatibility. The programmed value may be read
back in Offset 75 bits 5-4 (PCI Arbitration 1).