Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -33- Register Summary Tables
Technologies, Inc.
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Miscellaneous I/O
One I/O port is defined in the PLE133: Port 22.
Port 22 – PCI /AGP Arbiter Disable ................................RW
7-2 Reserved .........................................always reads 0
1 AGP Arbiter Disable
0 Respond to GREQ# signal..................... default
1 Do not respond to GREQ# signal
0 PCI Arbiter Disable
0 Respond to all REQ# signals ................. default
1 Do not respond to any REQ# signals,
including PREQ#
This port can be enabled for read/write access by setting bit-7
of Device 0 Configuration Register 78.
Configuration Space I/O
All registers in the PLE133 (listed above) are addressed via
the following configuration mechanism:
Mechanism #1
These ports respond only to double-word accesses. Byte or
word accesses will be passed on unchanged.
Port CFB-CF8 - Configuration Address..........................RW
31 Configuration Space Enable
0 Disabled ..................................................default
1 Convert configuration data port writes to
configuration cycles on the PCI bus
30-24 Reserved ......................................... always reads 0
23-16 PCI Bus Number
Used to choose a specific PCI bus in the system
15-11 Device Number
Used to choose a specific device in the system
(devices 0 and 1 are defined)
10-8 Function Number
Used to choose a specific function if the selected
device supports multiple functions (only function 0 is
defined).
7-2 Register Number (also called the "Offset")
Used to select a specific DWORD in the
configuration space
1-0 Fixed .........................................always reads 0
Port CFF-CFC - Configuration Data...............................RW
Refer to PCI Bus Specification Version 2.2 for further details
on operation of the above configuration registers.