Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -25- Register Summary Tables
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
Device 1 Bus 0 Registers - PCI-to-AGP Bridge
PCI Configuration Registers
Offset
Confi
g
uration Header Default Acc
1-0 Vendor ID
1106
RO
3-2 Device ID
8601
RO
5-4 Command
0007 RW
7-6 Status
0220 WC
8 Revision ID
nn
RO
9 Program Interface 00 RO
A Sub Class Code
04
RO
B Base Class Code
06
RO
C -reserved- (cache line size) 00 —
D Latency Timer 00
RW
E Header Type
01
RO
F Built In Self Test (BIST) 00 RO
10-17 -reserved- (base address registers) 00 —
18 Primary Bus Number 00
RW
19 Secondary Bus Number 00
RW
1A Subordinate Bus Number 00
RW
1B -reserved- (secondary latency timer) 00 —
1C I/O Base
F0 RW
1D I/O Limit 00
RW
1F-1E Secondary Status 0000 RO
21-20 Memory Base
FFF0 RW
23-22 Memory Limit (Inclusive) 0000
RW
25-24 Prefetchable Memory Base
FFF0 RW
27-26 Prefetchable Memory Limit 0000
RW
28-3D -reserved- (unassigned) 00 —
3F-3E PCI-to-AGP Bridge Control 00 RW
Device-Specific Configuration Registers
Offset
AGP Control Default Acc
40 CPU-to-AGP Flow Control 1 00 RW
41 CPU-to-AGP Flow Control 2 00 RW
42 AGP Master Control 00 RW
43-4F -reserved- (unassigned) 00 —