Product specifications
VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -24- Register Summary Tables
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
Device 0 Bus 0 Registers - Host Bridge
PCI Configuration Registers
Offset Confi
g
uration Header Default Acc
1
-
0
Ve
n
do
r ID
1106
RO
3
-
2
Device ID
0601
RO
5
-
4
Command
0006
RW
7
-
6
Status
0290
WC
8
Revision ID
nn
RO
9
Program Interface
00
RO
A
Sub Class Code
00
RO
B
Base Class Code
06
RO
C
-
reserved
-
(cache line size)
00
—
D
Latency Timer
00
RW
E
Header Type
00
RO
F
Built In Self Test (BIST)
00
RO
13
-
10
Graphics Aperture Base
0000 0008
RW
14
-
27
-
reserved
-
(base address registers)
00
—
28
-
2B
-
reserved
-
(unassigned)
00
—
2D
-
2C
Subsystem Vendor ID
0000
RW
2F
-
2E
Subsystem ID
0000
RW
33
-
30
-
reserved
-
(expan ROM base addr)
00
—
37
-
34
Capability Pointer
0000 00A0
RO
34
-
3B
-
reserved
-
(unassigned)
00
—
3C
-
3D
-
reserved
-
(interrupt line & pin)
00
—
3E
-
3F
-
reserved
-
(min gnt and max latency)
00
—
Device-Specific Configuration Registers
Offset CP
U
Interface Control Default Acc
50
Request Phase Control
02
RW
51
Response Phase Control
02
RW
52
Dynamic Defer Timer
10
RW
53
Miscellaneous
00
RW
55
-
54
Non
-
Cacheable Region #1
0000
RW
57
-
56
Non
-
Cacheable Region #2
0000
RW
Offset DRAM Control Default Acc
59
-
58
MA Map Type
0000
RW
5A
-
5F
DRAM Row Ending Address:
5A
Bank 0 Ending (HA[29:22])
01
RW
5B
Bank 1 Ending (HA[29:22])
01
RW
5C
Bank 2 Ending (HA[29:22])
01
RW
5D
Bank 3 Ending (HA[29:22])
01
RW
5E
Bank 4 Ending (HA[29:22])
01
RW
5F
Bank 5 Ending (HA[29:22])
01
RW
60
DRAM Type
00
RW
61
ROM Shadow Control C0000
-
CFFFF
00
RW
62
ROM Shadow Control D0000
-
DFFFF
00
RW
63
ROM Shadow Control E0000
-
FFFFF
00
RW
64
DRAM Timing for Banks 0,1
EC
RW
65
DRAM Timing for Banks 2,3
EC
RW
66
DRAM Timing for Banks 4,5
EC
RW
67
-
reserved
-
(unassigned)
00
RW
68
DRAM Control
00
RW
69
DRAM Clock Select
00
RW
6A
DRAM Refresh Counter
00
RW
6B
DRAM Arbitration Control
01
RW
6C
SDRAM Control
00
RW
6D
DRAM Control Drive Strength
00
RW
6E
-
6F
-
reserved
-
(unassigned)
00
—
Device-Specific Configuration Registers (continued)
Offset PCI Bus Control Default Acc
70
PCI Buffer Control
00
RW
71
CPU to PCI Flow Control 1
00
RW
72
CPU to PCI Flow Control 2
00
RW
73
PCI Master Control 1
00
RW
74
PCI Master Control 2
00
RW
75
PCI Arbitration 1
00
RW
76
PCI Arbitration 2
00
RW
77
Chip Test (do not program)
00
RW
78
PMU Control 1
00
RW
79
PMU Control 2
00
RW
7A
Miscellaneous Control
00
RW
7B
-
7D
-
reserved
-
00
—
7E
-
7F
DLL Test Mode (do not program)
00
RW
80
-
FF
-
reserved
-
00
—
Offset GART/TLB Control Default Acc
83
-
80
GART/TLB Control
0000 0000
RW
84
Graphics Aperture Size
00
RW
85
-
87
-
reserved
-
(unassigned)
00
—
8B
-
88
Gr. Aperture Translation Table Base
0000 0000
RW
8C
-
8F
-
reserved
-
(unassigned)
00
—
Offset AGP Control Default Acc
A0
AGP ID
02
RO
A1
AGP Next Item Pointer
00
RO
A2
AGP Specification Revision
10
RO
A3
-
reserved
-
(unassigned)
00
—
A7
-
A4
AGP Status
0700 0203
RO
AB
-
A8
AGP Command
0000 0000
RW
AC
AGP Control
00
RW
AD
AGP Latency
00
RW
AC
-
EF
-
reserved
-
(unassigned)
00
—
Offset BIOS Scratch Default Acc
F0-F7 BIOS Scratch 00 RW
Offset Miscellaneous Control Default Acc
F8 DRAM Arbitration Timer 1 00 RW
F9 DRAM Arbitration Timer 9 00 RW
FA CPU Direct Access FB Base Address 00 RW
FB Frame Buffer Conrol 00 RW
Offset Back Door Control Default Acc
FC Back Door Control 1 00 RW
FD Back Door Control 2 00 RW
FF
-
FE
Back Door Device ID
0000 0000
RW