Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -i- Revision History
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
R
EVISION
H
ISTORY
Document Release Date Revision Initials
0.92 12/9/98 Initial internal release DH
0.93 12/16/98 Updated pinouts to match engineering rev 0.5 document dated 12/1/98 DH
0.94 1/20/99 Updated pinouts to match engineering rev 0.8 document dated 12/22/98 DH
1.0 6/4/99 Added 133 MHz Support to Feature Bullets
Updated / Fixed Pin Descriptions: Fixed description of strap options on MA2, MA8,
and MA11-14; Removed Auxiliary Memory Port; Added REQ/GNT[4-7]#;
Added GND & VCC3 pins to increase pin count to 510 (updated mech spec);
Fixed definitions of RESET# & CRSTI# and changed CRSTI# to CPURSTD#;
Removed PWRGD function from SERR#; Fixed definitions of SRAS#, SCAS#,
and SWE#; Added note to PLLTST description
Updated Device 0 Rx50-53, 68[4], 69, 6B[5-1], 6C[7-4], 70[3,0, 72[0], 76[7], 79[1-
0], 7A (added); Device 1 Rx41[0], 42[0]
DH
1.1 6/23/99 Updated feature bullets & overview and fixed misc formatting problems
Fixed REQ/GNT4# pinouts and CKE & DQM naming polarity
Device 0 Bus 0 updated Rx2-3 Device ID, 69[7-6], 6D[6-5], 76[6]
Device 0 Bus 0 added Rx2C-D, 2E-F, 50[1], 51[5], 53[2], removed 6E-6F
Device 0 Bus 1 updated Rx0-3 Vendor & Device ID, Rx7-6[7]
Removed AC timing specs
DH
1.11 7/8/99 Fixed pin descriptions of CPURSTD# and SUSP DH
1.2 8/23/99 Fixed typo in device 0 Rx50[7] description; added comment about default state
Fixed system freq divider settings (MA pin descriptions, Dev 0 Rx68[1-0])
DH
1.3 9/8/99 Fixed strap options on MA2-6 and MA13 pin descriptions
Fixed Device 0 Rx52[7] strap option and removed (reserved) Device 0 Rx52[5]
Removed “VIA Confidential” watermark
DH
1.4 2/2/00 Added DSTN modes to intro/overview panel interface section
Removed incorrect notes under CPU interface pin descriptions
Fixed MA11 strapping and VCC3/VSUS3 pin descriptions
Fixed Device 0 Bus 0 Rx50[1] and Rx51[1] defaults
Fixed Electrical Specs absolute max temp ratings
DH
1.5 10/24/00 Changed product name to Apollo PLE133; Fixed typos in pinout table
Changed temp specs to be based on case instead of ambient; added power table
Changed orientation of pin 1 in mech diagram to match part marking
DH
1.6 11/1/00 Fixed product name on cover page; Fixed strap descriptions
Fixed Rx50[7], Rx68[1-0], 6B[4], 6C[4], D0Bus1 Rx4[9], Graphics CR39[0]
DH
1.7 12/1/00 Removed EDO, FP, VCM and PC66 DRAM support (no longer fully tested)
Added VIA Cyrix III CPU to suported CPUs list and changed 686A to 686B
Added PLLTST pin I/O type
Fixed table formatting errors introduced as a result of Word 2000 upgrade
Fixed Rx6B[4] and 6C[4]; Fixed spelling errors in Functional Description
DH
1.71 4/26/01 Fixed various typographical and formatting errors DH
1.8 7/3/01 Updated company address; updated processors list
Removed LVDS and direct panel drive support; removed MA3-6 straps
Fixed SUSP pin description; Fixed Device 0 Rx6A; moved VGA regs intro
DH
1.81 10/8/01 Clarified the difference between chipset name and north bridge part number
Changed “VIA Cyrix III” to “VIA C3”; Fixed max memory to be 1.5GB
Updated Device 0 Rx68[4], 69[7-6, 1], 6B[1]; Updated chip marking specs
DH
1.82 10/22/01 Fixed strap pin definitions for MA14,12,11 & updated Rx50[7], 68[1-0] to match DH