Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -19- Pinouts
Technologies, Inc.
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CRT Interface
Signal Name Pin # I/O Signal Description
RED
C2 A
Red. Red analog output to the CRT. Connect 75Ω load resistor to GNDR (RGB Return)
and connect to VGA connector through a series ferrite bead and 10pF capacitors to GNDR
on both input and output sides of the bead (see “Apollo PLE133 Design Guide”).
GRN
D3 A Green. Green analog output to the CRT. Connect same as RED.
BLUE
D2 A Blue. Blue analog output to the CRT. Connect same as RED.
HSYNC
E2 O Horizontal Sync. Digital horizontal sync output to the CRT. Also used (with VSYNC)
to signal power management state information to the CRT per the VESA™ DPMS™
standard. Connect to VGA connector through a series 47Ω resistor and 120pF capacitor
to ground (see “Apollo PLE133 Design Guide”).
VSYNC
E1 O Vertical Sync. Digital vertical sync output to the CRT. Also used (with HSYNC) to
signal power management state information to the CRT per the VESA™ DPMS™
standard. Connect to VGA connector through a series 47Ω resistor and 120pF capacitor
to ground (see “Apollo PLE133 Design Guide”).
SDA
F2 IO DDC Data/Address. Serial I
2
C protocol for VESA™ DDC2B signaling to the CRT.
Connect this pin to VCC5 through a 4.7KΩ pullup. Connect to the VGA connector only
(pin 12 of the connector). Connect through a ferrite bead and 120pF capacitor to ground
(on the output side of the bead). Refer to the “Apollo PLE133 Design Guide” for
additional information.
SCL
F3 IO DDC Clock. Serial I
2
C protocol for VESA™ DDC2B signaling to the CRT. Connect this
pin to VCC5 through a 4.7KΩ pullup. Connect to the VGA connector only (pin 15 of the
VGA connector). Connect through a ferrite bead and 120pF capacitor to ground (on the
output side of the bead). Refer to the “Apollo PLE133 Design Guide” for additional
information.
DFP Interface
Signal Name Pin # I/O Signal Description
PD[23-0]
(see pin list) O Panel Data. Digital pixel data outputs to the panel.
SCLK
G4 O Shift Clock. Clock for transferring digital pixel data.
DE
H3 O Data Enable. Indicates valid data on PD[23-0].
LP
G5 O Line Pulse. Digital monitor equivalent of HSYNC.
FLM
G3 O First Line Marker. Digital monitor equivalent of VSYNC.
EVDD
F1 O
Enable Panel VDD Power.
EVEE
H5 O
Enable Panel VEE Power.
EBLT
G1 O
Enable Panel Backlight.
Note: Connect SHFCLK, DE, LP, and FLM to external TMDS transmitters through series 22Ω resistors. See the “Apollo PLE133
Design Guide” for DFP interface design examples and additional information.