Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -18- Pinouts
Technologies, Inc.
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Clock / Reset Control
Signal Name Pin # I/O Signal Description
HCLK
G22 I Host Clock. This pin receives the host CPU clock. This clock is used by all logic in
the host CPU domain. It is driven by the external clock synthesizer.
MCLKI
K22 I Memory Clock In. This clock is used by internal clock logic to maintain the proper
phase relationship with MCLKO. It is driven by the external clock synthesizer.
MCLKO
J22 O Memory Clock Out. Created on-chip from MCLKI and used by the memory
controller as a timing reference for creation of all memory timing sequences. It is
connected to the external clock chip for use in maintaining proper phase relationships.
PCLK
AB15 I PCI Clock. This clock is used by all on-chip logic in the PCI clock domain. This input
must be 33 MHz maximum to comply with PCI specification requirements and must be
synchronous with the host CPU clock (HCLK) with an HCLK:PCLK frequency ratio of
2:1 (66MHz CPU clock) or 3:1 (100 MHz CPU clock). The PCI clock needs to be
controlled to within 1.5 ± 0.5 nsec relative to the host CPU clock (CPU leads).
PCKRUN#
AF15 IO PCI Clock Run. For implementation of PCI bus clock control for low-power PCI bus
operation. Refer to the “PCI Mobile Design Guidelines” and “Apollo PLE133 Design
Guide” documents for additional information.
XLTI
Y4 I Crystal Input. 14.31818 MHz for the video clock synthesizer reference. Connect to a
14.31818 MHz clock source if a crystal not used. Connect to main ground plane GND
with 10Pf if using a crystal.
XLTO
W4 O Crystal Output. 14.31818 MHz for the video clock synthesizer reference. Leave open
if a clock source is used instead of a crystal. Connect to main ground plane GND with
10Pf if using a crystal.
RESET#
AE15 I Reset. Driven from the South Bridge PCIRST# signal. When asserted (low), this
signal resets the PLE133 and sets all register bits to the default value. This signal also
connects to the PCI bus (South Bridge RESET drives the ISA bus if implemented). The
rising edge of this signal is used to sample all power-up strap options (see memory
interface MA pins).
CPURST#
A19 O CPU Reset. CPU Reset output to the host CPU.
CPURSTD#
E22 O CPU Reset Delayed 2T. Alternate CPU Reset output to the host CPU
PWROK
AD14 I Power OK. Connect to South Bridge and Power Good circuitry.
SUST#
AC22 I Suspend Status. For implementation of the Suspend-to-DRAM feature. Input logic for
this pin is powered by VSUS. Connect to the South Bridge SUST# pin or to a 10KΩ
pullup to VSUS if not used.
SUSP
F5 I Suspend. Used to put the integrated graphics controller into suspend state. Input logic
for this pin is powered by VCC3. Connect to South Bridge GPO pin or to a 10KΩ
pullup to VCC3 if not used.
Miscellaneous
Signal Name Pin # I/O Signal Description
ETST#
F4 I
Test Mode Enable. 4.7KΩ pullup to VCC3 for normal operation.
IMIO
M2 O IMI Out. Leave open.
IMIIN
M3 I
IMI In. 4.7KΩ pullup to VCC3.