Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -17- Pinouts
Technologies, Inc.
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PCI Bus Interface
Signal Name Pin # I/O Signal Description
AD[31:0]
see pin list IO Address/Data Bus. The standard PCI address and data lines. The address is
driven with FRAME# assertion and data is driven or received in following
cycles.
CBE[3:0]#
AD7, AD9, AB11,
AF12
IO Command/Byte Enables. Commands are driven with FRAME# assertion.
Byte enables corresponding to supplied or requested data are driven on
following clocks.
PAR
AB10 IO Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0].
FRAME#
AE9 IO Frame. Assertion indicates the address phase of a PCI transfer. Negation
indicates that one more data transfer is desired by the cycle initiator. 10KΩ
pullup to VCC3.
IRDY#
AC10 IO
Initiator Ready. Asserted when initiator is ready for data transfer. 10KΩ
pullup to VCC3.
TRDY#
AD10 IO
Target Ready. Asserted when target is ready for data transfer. 10KΩ pullup to
VCC3.
STOP#
AE10 IO Stop. Asserted by the target to request the master to stop the current
transaction. 10KΩ pullup to VCC3.
DEVSEL#
AB9 IO Device Select. This signal is driven by the PLE133 when a PCI initiator is
attempting to access main memory. It is an input when the PLE133 is acting as
a PCI initiator. 10KΩ pullup to VCC3.
LOCK#
AE5 IO
Lock. Used to establish, maintain, and release resource lock. 10KΩ pullup to
VCC3.
SERR#
AF10 IO System Error. The PLE133 will pulse this signal when it detects a system
error condition (10KΩ pullup to VCC3).
PREQ#
AC15 I South Bridge Request. This signal comes from the South Bridge. PREQ# is
the South Bridge request for the PCI bus. 10KΩ pullup to VCC3.
PGNT#
AD15 O South Bridge Grant. This signal driven by the PLE133 to grant PCI access to
the South Bridge. 10KΩ pullup to VCC3.
REQ[7:0]#
AD1, AC3, AC2, AF2,
AD4, AE4, AD5, AC5
I
PCI Master Request. PCI master requests for use of the PCI bus. 2.2KΩ
pullup to VCC5.
GNT[7:0]#
AE1, AD3, AD2,
AE2, AE3, AF3, AF4,
AB5
O PCI Master Grant. Permission is given to the master to use the PCI bus.
2.2KΩ pullup to VCC3.
INTA#
W5 O PCI Interrupt Out. INTA# is an asynchronous active low output used to
signal an event that requires handling. It is driven by the integrated graphics
controller.
Note: Clocking of the PCI interface is performed with PCLK; see the clock pin group at the end of the pin descriptions section for
descriptions of the clock input pins.