Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -15- Pinouts
Technologies, Inc.
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PIN DESCRIPTIONS
Table 1. VT8601A Pin Descriptions
CPU Interface
Signal Name Pin # I/O Signal Description
HA[31:3]#
see pin list IO Host Address Bus. Connect to the address bus of the host CPU. These pins are inputs
during CPU cycles, but are driven by the VT8601A during cache snooping operations.
HD[63:0]#
see pin list IO Host CPU Data. These signals are connected to the CPU data bus.
ADS#
J24 IO Address Strobe. The CPU asserts ADS# in T1 of the CPU bus cycle.
BNR#
D26 IO Block Next Request. Used to block the current request bus owner from issuing new
requests. This signal is used to dynamically control the processor bus pipeline depth.
BPRI#
E26 IO Priority Agent Bus Request. The owner of this signal will always be the next bus owner.
This signal has priority over symmetric bus requests and causes the current symmetric
owner to stop issuing new transactions unless the HLOCK# signal is asserted. The
VT82C693 drives this signal to gain control of the processor bus.
DBSY#
H26 IO Data Bus Busy. Used by the data bus owner to hold the data bus for transfers requiring
more than one cycle.
DEFER#
F26 IO Defer. The VT8601A uses a dynamic deferring policy to optimize system performance.
The VT8601A also uses the DEFER# signal to indicate a processor retry response.
DRDY#
J23 IO Data Ready. Asserted for each cycle that data is transferred.
HIT#
G24 IO Hit. Indicates that a cacheing agent holds an unmodified version of the requested line.
Also driven in conjunction with HITM# by the target to extend the snoop window.
HITM#
G26 I Hit Modified. Asserted by the CPU to indicate that the address presented with the last
assertion of EADS# is modified in the L1 cache and needs to be written back.
HLOCK#
G23 I Host Lock. All CPU cycles sampled with the assertion of HLOCK# and ADS# until the
negation of HLOCK# must be atomic.
BREQ0#
J25 O Bus Request 0. Bus request output to CPU.
HREQ[4:0]#
E25, F25,
F24, F23,
E24
IO Request Command. Asserted during both clocks of the request phase. In the first clock,
the signals define the transaction type to a level of detail that is sufficient to begin a snoop
request. In the second clock, the signals carry additional information to define the
complete transaction type.
HTRDY#
G25 IO Host Target Ready. Indicates that the target of the processor transaction is able to enter
the data transfer phase.
RS[2:0]#
H25, K23,
H23
IO Response Signals. Indicates the type of response per the table below:
RS[2:0]#
Response type
000 Idle State
001 Retry Response
010 Defer Response
011 Reserved
100 Hard Failure
101 Normal Without Data
110 Implicit Writeback
111 Normal With Data
CPURST#
A19 O CPU Reset. Reset output to CPU
CPURSTD#
E22 O CPU Reset Delayed. CPU Reset output delayed by 2T.