Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -7- System Overview
Technologies, Inc.
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Apollo PLE133 Core Logic Overview
The Apollo PLE133 chipset is a high performance, cost-effective and energy efficient solution for the implementation of
Integrated 2D / 3D Graphics - PCI - ISA desktop and notebook personal computer systems from 66 MHz to 133 MHz based on 64-
bit Socket-370 VIA C3 / Intel Celeron and Pentium III processors. The complete solution consists of the VT8601A “System
Media Accelerator” (SMA) north bridge (510 BGA) and either the VT82C596B (324 BGA) or the VT82C686B (352 BGA) PCI-
to-ISA south bridge. Both south bridges are PC98 / PC99 compliant with integrated UltraDMA-66 / 33 IDE, 4 USB ports, and a
complete power management feature set. The VT82C686B also integrates HW monitoring, Super-I/O functions (floppy disk drive
interface and serial / parallel ports), and AC-97 link supporting digital audio and HSP modem functions.
Apollo PLE133 supports six banks of DRAMs up to 1.5GB. The DRAM controller supports PC133 and PC100 Synchronous
DRAM (SDRAM). The Synchronous DRAM interface allows zero wait state bursting between the DRAM and the data buffers at
100 or 133 MHz. The six banks of DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M / 32MxN
DRAMs. The DRAM Controller is optimized to run synchronous with the CPU Front Side Bus (FSB) frequency of 100 or 133
MHz or pseudosynchronous to the Front Side Bus with the SDRAM and FSB frequencies differing by 33 MHz.
Apollo PLE133 also supports full AGP v1.0 capability with the internal 2D/3D Graphics Engine for maximum software
compatibility. An eight level request queue plus a four level post-write request queue with thirty-two and sixteen quadwords of
read and write data FIFO’s respectively are included for deep pipelined and split AGP transactions. A single-level GART TLB
with 16 full associative entries and flexible CPU/AGP/PCI remapping control is also provided for operation under protected mode
operating environments. Both Windows-95 VXD and Windows-98 / NT5 miniport drivers are supported.
Apollo PLE133 supports one 32-bit 3.3 / 5V system bus (PCI) that is synchronous to the CPU bus. The chip also contains a built-
in AGP bus-to-PCI bus bridge to allow simultaneous concurrent operations on each bus. Five levels (doublewords) of post write
buffers are included to allow for concurrent CPU and PCI operation. For PCI master operation, forty-eight levels (doublewords)
of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for concurrent PCI bus and DRAM/cache
accesses. The chip also supports enhanced PCI bus commands such as Memory-Read-Line, Memory-Read-Multiple and Memory-
Write-Invalid commands to minimize snoop overhead. In addition, advanced features are supported such as snoop ahead, snoop
filtering, L1 / L2 write-back forward to PCI master, and L1 / L2 write-back merged with PCI post write buffers to minimize PCI
master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also implemented for further
improvement of overall system performance.
For sophisticated notebook implementations, the Apollo PLE133 north bridge provides independent clock stop control for the CPU
/ SDRAM, PCI, and AGP buses and Dynamic CKE control for powering down of the SDRAM. A separate suspend-well plane is
implemented for the SDRAM control signals for Suspend-to-DRAM operation. Coupled with the 324-pin Ball Grid Array VIA
VT82C596B south bridge chip, a complete notebook PC main board can be implemented with no external TTLs.