Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -114 3D Graphics Engine Registers
Technologies, Inc.
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GEbase + 24 – Graphics Engine Control........................ WO
7 Reset
0 Normal operation ................................... default
1 Reset all internal registers and pointers. Reset
is performed by setting this bit to 1 and then
back to 0.
6-4 Reserved .........................................always reads 0
3-0 Debug Module Select ................................default = 0
Module to Debug
GE Register 28
000 None undefined
001 Setup Engine SE Status
010 Rasterization Engine RE Status
011 Pixel Engine PE Status
100 Memory Interface MI Status
101 Cmd List Ctrl Unit Cmd List Start Address
110 Cmd List Ctrl Unit Cmd List End Address
111 -reserved- n/a
GEbase + 28 – Graphics Engine Debug ........................... RO
31-0 Engine Module Status
(See register 24 bits 3-0 above)
GEbase + 2C – Graphics Engine Wait Mask..................RW
31-0 Wait Mask
When writing to this register, hardware will monitor
the value of M (Wait Mask & Status). If M is not 0,
the Graphics Engine (including the RE, SE, PE, and
MI) will not accept new registers from the host CPU
or AGP bus. This register is cleared by the hardware
when M = 0. Only bits 31-28, 26, 23, and 21-20 are
effective (all other bits are ignored).