Product specifications

VT8601A Apollo PLE133
Revision 1.82 October 22, 2001 -112 3D Graphics Engine Registers
Technologies, Inc.
Delivering Value
Delivering ValueDelivering Value
Delivering Value
Graphics Engine Core
GEbase + 10 - Right View Display Base Address ...........RW
31 Right View Active
0 Inactive (use VGA style for display start
address) .................................................. default
1 Active (use the base register address in this
register for the display starting address)
30-24 Reserved .........................................always reads 0
23-0 Right View Display Starting Address
Writing to this register sets Status Register bit-21 to 0. Later
when the address is used to display a frame, the status bit is
changed to 1.
GEbase + 14 - Left View Display Base Address..............RW
31 Left View Active
0 Disable (only Right View Display Starting
Address is used) ..................................... default
1 Enable (Right View Display Starting Address
is used for the right view and this register for
the left view; hardware will use these two
addresses alternately)
30-24 Reserved .........................................always reads 0
23-0 Left View Display Starting Address
Writing to this register sets Status Register bit-20 to 0. Later
when the address is used to display a frame, the status bit is
changed to 1.
GEbase + 18 – Block Write Start Address ......................RW
31 Linear Mode
0 Fill a rectangle area.................................default
1 Fill a linear area
30-24 Reserved ......................................... always reads 0
23-0 Starting Address (in multiples of 64 bytes)
GEbase + 1C – Block Write Area / End Address ...........RW
Rectangle Area Fill Mode
31-28 Reserved ......................................... always reads 0
27-16 Height of the Area
15-12 Reserved ......................................... always reads 0
11-0 Width of the Area (in bytes)
Stride is Destination Stride in port 21C0h
Linear Area Fill Mode
31-0 End Address (in multiples of 64 bytes inclusive)
Writing to this register triggers a Memory Set operation.
Color for this operation is specified in the Foreground register.