VIA Technologies Delivering Value Apollo PLE133 Chipset VT8601A North Bridge Single-Chip Socket-370 PCI North Bridge with 133 / 100 / 66 MHz Front Side Bus, Integrated AGP 2D / 3D Graphics Accelerator and Advanced Memory Controller supporting PC133 / PC100 SDRAM for Desktop PC Systems Revision 1.82 October 22, 2001 VIA TECHNOLOGIES, INC.
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Technologies, Inc. VT8601A Apollo PLE133 Delivering Value REVISION HISTORY Document Release 0.92 0.93 0.94 1.0 1.1 1.11 1.2 1.3 1.4 1.5 1.6 1.7 1.71 1.8 1.81 1.82 Date 12/9/98 12/16/98 1/20/99 6/4/99 Revision Initial internal release Updated pinouts to match engineering rev 0.5 document dated 12/1/98 Updated pinouts to match engineering rev 0.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value TABLE OF CONTENTS REVISION HISTORY.......................................................................................................................................................................... I TABLE OF CONTENTS.................................................................................................................................................................... II LIST OF FIGURES ...........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Attribute Controller Registers (AR)....................................................................................................................................................69 VGA Status / Enable Registers ...........................................................................................................................................................69 VGA Sequencer Registers (SR).................................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value LIST OF FIGURES FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. FIGURE 7. FIGURE 8. FIGURE 9. VT8601A BALL DIAGRAM (TOP VIEW)................................................................................................................12 VT8601A PIN LIST (NUMERICAL ORDER) ..........................................................................................................13 VT8601A PIN LIST (ALPHABETICAL ORDER) ................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value VIA VT8601A Apollo PLE133 133 / 100 / 66 MHz Single-Chip Socket-370 PCI North Bridge, With Integrated AGP 2D / 3D Graphics Accelerator and Advanced Memory Controller supporting PC133 / PC100 SDRAM For Desktop PC Systems PRODUCT FEATURES • General − 510 BGA Package (35mm x 35mm ) − 2.5 Volt core with 3.3V CMOS I/O − Supports GTL+ I/O buffer Host interface − Supports separately powered 5.0V tolerant interface to PCI bus and Video interface − 2.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value • Internal Accelerated Graphics Port (AGP) Controller − AGP v1.
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Technologies, Inc. VT8601A Apollo PLE133 Delivering Value • DVD − Hardware-Assisted MPEG-2 Architecture for DVD with AC-3 − Simultaneous motion compensation and front-end processing (parsing, decryption and decode) − Supports full DVD 1.0, VCD 2.0 and CD-Karaoke − Microsoft DirectShow 3.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value SYSTEM OVERVIEW The Apollo PLE133 chipset consists of the VT8601A North Bridge (described by this document) and the VT82C686B South Bridge (described in a separate data sheet). The VT8601A is a PC system logic North Bridge for Socket-370 CPUs with integrated 2D/3D Graphics accelerator. The core logic portion of the chip is based on the VIA Apollo Pro133 with integrated graphics accelerator provided by an industry leading Graphics supplier.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Apollo PLE133 Core Logic Overview The Apollo PLE133 chipset is a high performance, cost-effective and energy efficient solution for the implementation of Integrated 2D / 3D Graphics - PCI - ISA desktop and notebook personal computer systems from 66 MHz to 133 MHz based on 64bit Socket-370 VIA C3 / Intel Celeron and Pentium III processors.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Apollo PLE133 Graphics Controller Overview The Apollo PLE133 Graphics Controller is a highly integrated display control device that incorporates a 64-bit 3D/2D graphic engine and video accelerator with advanced DVD video and optional TV output capability. It provides a flexible and high performance solution for graphics and video playback acceleration for various color depth and resolution modes.
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Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Video Processor Video processor features include: on-chip hardware Color Space Conversion (CSC) for faster data conversion on the fly, Horizontal/Vertical (H/V) scaling with interpolation, edge recovery algorithm logic, gamma correction, and overlay control with different color depths from graphics.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value CRT Power Management (VESA DPMS) The Apollo PLE133 Graphics Controller conforms to the standard power management schemes defined by VESA™ for CRTs. The Apollo PLE133 Graphics Controller supports four states of VESA™ Display Power Management Signaling (DPMS), which decrease monitor power consumption after timeout periods.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value PINOUTS Figure 1.
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Technologies, Inc. VT8601A Apollo PLE133 Delivering Value PIN DESCRIPTIONS Table 1. VT8601A Pin Descriptions CPU Interface Signal Name Pin # I/O Signal Description HA[31:3]# see pin list IO HD[63:0]# ADS# BNR# see pin list J24 D26 IO IO IO BPRI# E26 IO DBSY# H26 IO DEFER# F26 IO DRDY# HIT# J23 G24 IO IO HITM# G26 I HLOCK# G23 I J25 E25, F25, F24, F23, E24 O IO HTRDY# G25 IO RS[2:0]# H25, K23, H23 IO A19 E22 O O Host Address Bus.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value DRAM Interface Signal Name Pin # I/O Signal Description MD[63:0] MA[14:0] / Strap Options see pin list AF25, AE25, AE24, AD24, AE26, AD25, AD26, AC24, AC25, AC26, AB24, AB25, AB26, AB23, AA23 IO O/I CKE5# / SRASB#, CKE4# / SRASC#, CKE3# / SCASB#, CKE2# / SWEB#, CKE1# / SCASC#, CKE0# / SWEC# CS[5-0]# AA25, AA26, V25, U25, V24, U26 W21, Y22, Y23, Y24, Y25, Y26 AF23, AD23, W25, W26, AE23, AF24, W23, V23 AA24, AA25, AA26 IO Memory Data.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value PCI Bus Interface Signal Name Pin # I/O Signal Description see pin list IO CBE[3:0]# AD7, AD9, AB11, AF12 IO PAR FRAME# AB10 AE9 IO IO IRDY# AC10 IO TRDY# AD10 IO STOP# AE10 IO DEVSEL# AB9 IO LOCK# AE5 IO SERR# AF10 IO PREQ# AC15 I PGNT# AD15 O AD1, AC3, AC2, AF2, AD4, AE4, AD5, AC5 AE1, AD3, AD2, AE2, AE3, AF3, AF4, AB5 W5 I Address/Data Bus. The standard PCI address and data lines.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Clock / Reset Control Signal Name Pin # I/O HCLK G22 I MCLKI K22 I MCLKO J22 O PCLK AB15 I PCKRUN# AF15 IO XLTI Y4 I XLTO W4 O RESET# AE15 I CPURST# CPURSTD# PWROK SUST# A19 E22 AD14 AC22 O O I I F5 I SUSP Signal Description Host Clock. This pin receives the host CPU clock. This clock is used by all logic in the host CPU domain. It is driven by the external clock synthesizer. Memory Clock In.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value CRT Interface Signal Name Pin # I/O RED C2 A GRN BLUE HSYNC D3 D2 E2 A A O VSYNC E1 O SDA F2 IO SCL F3 IO Signal Description Red. Red analog output to the CRT. Connect 75Ω load resistor to GNDR (RGB Return) and connect to VGA connector through a series ferrite bead and 10pF capacitors to GNDR on both input and output sides of the bead (see “Apollo PLE133 Design Guide”). Green. Green analog output to the CRT. Connect same as RED.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value TV Input / Video Interface Signal Name Pin # I/O Signal Description N4, N1, N2, N5, P4, P3, P2, P5, IO Video Capture / Playback Data. R3, R1, R4, R2, R5, T1, T2, R6 T3 IO Video Horizontal Sync. Connect to TV decoder if used. VHS U1 IO Video Vertical Sync. Connect to TV decoder if used. VVS U3 IO Video Clock. Connect to TV decoder through a series 22Ω resistor.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Clock Power / Ground and Filtering Signal Name Pin # I/O VCCA H21, H22 P GNDA L21, L22 P VCCV1 W2 P GNDV1 Y1 P VLF1 Y3 A VCCV2 Y2 P GNDV2 AA1 P VLF2 AA2 A PLLTST K24 I Signal Description Power for North Bridge Clock Circuitry (2.5V ±5%). Connect to VCCI through a ferrite bead and decouple to GNDA with 0.001Uf and 0.1Uf ceramic and 10Uf tantalum capacitors (see “Apollo PLE133 Design Guide”).
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Technologies, Inc. VT8601A Apollo PLE133 Delivering Value REGISTERS Register Overview Register Summary Tables The following tables summarize the configuration and I/O registers of the PLE133. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’s to Clear individual bits).
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Technologies, Inc. VT8601A Apollo PLE133 Delivering Value 3D Graphics Engine Registers These registers are addressed at offsets from the Graphics Engine Base Address (GEbase). All registers are 32-bit.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Miscellaneous I/O Configuration Space I/O One I/O port is defined in the PLE133: Port 22. All registers in the PLE133 (listed above) are addressed via the following configuration mechanism: Port 22 – PCI /AGP Arbiter Disable ................................RW 7-2 Reserved .........................................always reads 0 1 AGP Arbiter Disable 0 Respond to GREQ# signal.....................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Register Descriptions Device 0 Offset 7-6 - Status ............................................RWC 15 Detected Parity Error 0 No parity error detected ..........................default 1 Error detected in either address or data phase. This bit is set even if error response is disabled (command register bit-6). ......write one to clear 14 Signaled System Error (SERR# Asserted) .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Offset E - Header Type....................................... RO 7-0 Header Type Code ............reads 00: single function Device 0 Offset 2D-2C – Subsystem Vendor ID ..............RW 15-0 Subsystem Vendor ID......................... default = 0000 Device 0 Offset F - Built In Self Test (BIST) ................... RO 7 BIST Supported ......reads 0: no supported functions 6-0 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Bus 0 Host Bridge Registers CPU Interface Control Device 0 Offset 50 – Request Phase Control (02h)..........RW 7 CPU Hardwired IOQ (In Order Queue) Size Default per the strap on pin MA11 during reset. This register bit can be written to 1 to restrict the chip to one level of IOQ. 0 4-Level ...... default if no external strap resistor 1 1-Level 6 Read-Around-Write 0 Disable ...................................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Offset 52 – Dynamic Defer Timer (10h) ...........RW 7 GTL I/O Buffer Pullup........... default = MA13 Strap 0 Disable 1 Enable The default value of this bit is determined by a strap on the MA13 pin during reset. 6 RAW Write Retire After 2 Writes 0 Disable ................................................... default 1 Enable 5 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Offset 55-54 - Non-Cacheable Region #1 ..........RW 15-3 Base Address - A<28:16>............................ default=0 As noted below, the base address must be a multiple of the region size. 2-0 Range (Region Size) 000 Disable ...................................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value DRAM Control Device 0 Offset 5A-5F – DRAM Row Ending Address: All of the registers in this group default to 01h: These registers are normally set at system initialization time and not accessed after that during normal system operation.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Offset 61 - Shadow RAM Control 1 ..................RW 7-6 CC000h-CFFFFh 00 Read/write disable.................................. default 01 Write enable 10 Read enable 11 Read/write enable 5-4 C8000h-CBFFFh 00 Read/write disable.................................. default 01 Write enable 10 Read enable 11 Read/write enable 3-2 C4000h-C7FFFh 00 Read/write disable..................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Offset 64 - DRAM Timing for Banks 0,1..........RW Device 0 Offset 65 - DRAM Timing for Banks 2,3..........RW Device 0 Offset 66 - DRAM Timing for Banks 4,5..........RW Settings for Registers 64-66 7 Precharge Command to Active Command Period 0 TRP = 2T 1 TRP = 3T ................................................ default 6 Active Command to Precharge Command Period 0 TRAS = 5T 1 TRAS = 6T ..............................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Offset 69 – DRAM Clock Select (00h)...............RW 7-6 DRAM Operating Frequency Select .................. RW Rx68[1-0] Rx69[7-6] Rx68[4] CPU/DRAM/VGA 00 00 x 66/66/66 (default) 00 01 x 66/100/100 01 00 x 100/100/100 01 10 x 100/66/66 01 01 1 100/133/133 10 00 1 133/133/133 10 10 x 133/100/100 All other combinations are reserved.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Offset 6C - SDRAM Control..............................RW 7-5 Reserved .........................................always reads 0 4 CKE Configuration 0 RASA = CSA, RASB = CSB, CKE0=CKE0, CKE1 = CKE1 1 RASA = CSA, RASB = CSB, CKE3-2 = CSA7-6 CKE5-4 = CSB7-6 CKE1 = GCKE (Global CKE) CKE0 = FENA (FET Enable) 3 Fast AGP TLB lookup 0 Disable ...................................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value PCI Bus Control These registers are normally programmed once at system initialization time. Device 0 Offset 70 - PCI Buffer Control ..........................RW 7 CPU to PCI Post-Write 0 Disable ................................................... default 1 Enable 6 PCI Master to DRAM Post-Write 0 Disable ................................................... default 1 Enable 5 Reserved 4 PCI Master to DRAM Prefetch Disable 0 Enable...................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Offset 72 - CPU to PCI Flow Control 2 .........RWC 7 Retry Status 0 Retry occurred less than retry limit........ default 1 Retry occurred more than x times (where x is defined by bits 5-4) ..................write 1 to clear 6 Retry Timeout Action 0 Retry Forever (record status only) ......... default 1 Flush buffer for write or return all 1s for read 5-4 Retry Limit 00 Retry 2 times ..........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Offset 75 - PCI Arbitration 1 .............................RW 7 Arbitration Mechanism 0 PCI has priority ...................................... default 1 Fair arbitration between PCI and CPU 6 Arbitration Mode 0 REQ-based (arbitrate at end of REQ#) .. default 1 Frame-based (arbitrate at FRAME# assertion) 5-4 Latency Timer ...........
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Offset 78 - PMU Control 1 .................................RW 7 I/O Port 22 Access 0 CPU access to I/O address 22h is passed on to the PCI bus ............................................. default 1 CPU access to I/O address 22h is processed internally 6 Suspend Refresh Type 0 CBR Refresh .......................................... default 1 Self Refresh 5 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GART / Graphics Aperture Control The function of the Graphics Address Relocation Table (GART) is to translate virtual 32-bit addresses issued by an AGP device into 4K-page based physical addresses for system memory access. In this translation, the upper 20 bits (A31A12) are remapped, while the lower 12 address bits (A11-A0) are used unchanged.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Offset 83-80 - GART/TLB Control ...................RW 31-16 Reserved .........................................always reads 0 15-8 Reserved (test mode status)..................................RO 7 Flush Page TLB 0 Disable ................................................... default 1 Enable 6-4 Reserved (always program to 0)......................... RW Device 0 Offset 84 - Graphics Aperture Size...................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value AGP Control Device 0 Offset A3-A0 - AGP Capability Identifier........ RO 31-24 Reserved .......................................always reads 00 23-20 Major Specification Revision ......always reads 0001 Major revision # of AGP spec device conforms to 19-16 Minor Specification Revision ......always reads 0000 Minor revision # of AGP spec device conforms to 15-8 Pointer to Next Item ....... always reads 00 (last item) 7-0 AGP ID ..
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Offset F7-F0 – BIOS Scratch Register..............RW 7-0 No Hardware Function Device 0 Offset FC – Back Door Control 1......................RW 7-2 Reserved ......................................... always reads 0 1 Back-Door Max # of AGP Requests Allowed 0 Read RXA7 will return 7........................default 1 Read RxXA7 will have number programmed at RxFD 0 Back-Door Device ID Enable 0 Use Rx3-2’s value for Rx3-2 read..........
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 1 Bus 0 Header Registers - PCI-to-AGP Bridge Device 1 Offset 7-6 - Status (Primary Bus)...................RWC 15 Detected Parity Error......................... always reads 0 14 Signaled System Error (SERR#)....... always reads 0 13 Signaled Master Abort 0 No abort received....................................default 1 Transaction aborted by the master with Master-Abort (except Special Cycles)............... ................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 1 Offset 18 - Primary Bus Number ......................RW 7-0 Primary Bus Number ............................... default = 0 This register is read write, but internally the chip always uses bus 0 as the primary. Device 1 Offset 3F-3E – PCI-to-PCI Bridge Control .....RW 15-4 Reserved ......................................... always reads 0 3 VGA-Present on AGP 0 Forward VGA accesses to PCI Bus........
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 1 Bus 0 PCI-to-AGP Bridge Registers Device 1 Offset 41 - CPU-to-AGP Flow Control 2.......RWC 7 Retry Status 0 No retry occurred ....................................default 1 Retry Occurred.........................write 1 to clear 6 Retry Timeout Action 0 No action taken except to record status ........def 1 Flush buffer for write or return all 1s for read 5-4 Retry Count 00 Retry 2, backoff CPU .............................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Bus 1 Header Registers - Graphics Accelerator The Apollo PLE133 2D / 3D Graphics Accelerator is fully compliant with PCI bus interface protocol revision 2.2. The controller implements slave functions of PCI to accept cycles initiated by PCI masters targeted for its internal registers, RAMDAC™, frame buffer, and/or BIOS.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Offset 5-4 - Command........................................................RW 15-10 Reserved .........................................always reads 0 9 Fast Back-to-Back Cycle Enable .........................RO 0 Fast back-to-back transactions only allowed to the same agent 1 Fast back-to-back transactions allowed to different agents 8 SERR# Enable.......................................................RO 0 SERR# driver disabled....................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Offset 8 - Revision ID ......................................................... RO 8-0 VT8601A Graphics Controller Revision Code Offset 3C – Interrupt Line ................................................RW 7-0 Interrupt Line .......................................default = 0Bh Offset 9 - Programming Interface .................................... RO 7-0 Interface Identifier............................always reads 00 Offset 3D – Interrupt Pin .
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Device 0 Bus 1 Graphics Accelerator Registers Offset 93-90 – Power Management 1................................ RO 31-27 Reserved .........................................always reads 0 PME# not supported 26 D2 State (Suspend) Supported...........always reads 1 The D2 state is supported 25 D1 State (Standby) Supported...........always reads 1 The D1 state is supported 24-22 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Graphics Accelerator PCI Bus Master Registers Port 2300 – Graphics Bus Master Control ......................RW 31-16 Reserved ......................................... always reads 0 15 PCI Master Read Data to GE SRCQ 0 Disable ....................................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Port 2310 – Graphics Bus Master System Start Addr ...RW 31-0 System Start Address If scatter / gather is enabled, bits 31:12 point to the physical region translation table (the page starting address must be aligned on 4KB address boundaries) and bits 11:0 are the offset within a page. Port 2314 – Graphics Bus Master Height........................RW 15-10 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Graphics Accelerator AGP Registers Command List Format The command list is stored in AGP memory in groups. Each group has the following format: Bit Bit 63 48 32 31 16 0 QuadWord 0 Data 0 Header 1 Data 2 Data 1 2 Data 4 Data 3 … … … n/2+1 Pad/Data n-1 Data n – 1/2 The header is a 32-bit word that contains information about this group, such as the amount of useful data in the group. A group is always padded to a quadword boundary.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Port 2348 – Graphics AGP Channel 1 FB Start/Pitch ...RW 31-22 Frame Buffer Line Offset (in quadwords) 21-19 Reserved .........................................always reads 0 18-0 Frame Buffer Starting Address Port 2364 –Channel Arbitration Counter Threshold.....RW 31-28 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Port 236C – Graphics AGP Global & Chan 2 Control ..RW 31-26 Reserved .........................................always reads 0 25-24 Sideband Address (SBA) Standby Latency Timer 23 High Priority Command Enable 0 Disable ................................................... default 1 Enable 22 Long Read Command Enable 0 Disable ...................................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Command List Operation Capture / ZV Port Registers The PLE133 implements an internal block called the “Command List Control Unit” to process command lists. Command list operation is invisible to software. After initialization of the Command List Control Unit, software can set registers as if there is no Command List Control Unit.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value DVD Registers Port 2280 – MC Version ID............................................... RO 7-0 Version ID Port 2282 – MC Frame Buffer Configuration.................RW 7 Interlaced Display 6 TV Flicker Filter Bypass 0 Use TV CRTC ........................................default 1 Use VGA CRTC 5 Request Threshold of Display Command Queue 4 Request Threshold of PBF 3 Request Threshold of PFF 2 Hardware SP RL-Decode Disable 0 Enable ...................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Port 2287-2284 – MC Command Queue ..........................RW 31-12 Page Table Address Port 2285-2284 – MC Status .............................................RW 15 Task Pop Out Done Status 14-12 FIFO Status 11 SP Command Present 0 SP Command is Absent ......................... default 1 SP Command is Present 10-9 Video Output Display Fields 00 -reserved- ...............................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Port 228B-2288 – MC Y-Reference Address ...................RW 31-20 Reserved .........................................always reads 0 19-0 Y-Reference Start Address (quadword aligned) Port 22AB-22A8 – Color Palette Entries .........................RW Port 228F-228C – MC U-Reference Address ..................RW 31-20 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value groups except the Attribute Controller (due to the unusual nature of Attribute Controller indexing using a single I/O port which makes access to this register group more cumbersome). This document will detail the functions of all the standard VGA registers first. All extended functions will then be separately documented in following sections.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Attribute Controller Registers (AR) VGA Status / Enable Registers For this indexed register group, the index is accessed at 3C0 as expected. However, although data operations can be performed using port 3C1 in the standard way, data is generally accessed at 3C0 as well. In other words, data and address are accessed on alternate operations to 3C0 with an internal flag to keep track of where the next operation is to be performed.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value VGA Sequencer Registers (SR) VGA RAMDAC Registers Port 3C4 – VGA Sequencer Index....................................RW 7-0 Sequencer Index Only the lower 3 bits are implemented in a standard VGA to point to Sequencer registers 0-4. However, all 8 bits are implemented here to allow for extended registers up to index FF. Port 3C6 – VGA RAMDAC Pixel Mask..........................RW 7-0 Palette Address Mask Port 3C6 – VGA RAMDAC Command...........
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value VGA Graphics Controller Registers (GR) Port 3CE – VGA Graphics Controller Index ..................RW 7 Reserved .........................................always reads 0 6-0 Graphics Controller Index Only the lower 4 bits are implemented in a standard VGA to allow access to Graphics Controller registers 0-8. However, 7 bits are implemented here to allow for extended registers up to index 7F. Port 3CF Index 5 – Graphics Controller Mode .............
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Port 3x5 Index A – VGA CRTC – Cursor Start .............RW 7-6 Reserved ......................................... always reads 0 5 Cursor On/Off........................................... default = 0 4-0 Cursor Row Scan Start ............................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value VGA Extended Registers VGA Extended Registers – Non-Indexed I/O Ports Port 3xB – Alternate Clock Select ....................................RW 3xB notation indicates that this register is accessible at either 3BB or 3DB depending on the setting of the color / mono bit. 7-5 New Mode Control Register Bits 3-1 .......... def = 00 These bits have the same function as SRD[3-1] 4-2 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value VGA Extended Registers – Sequencer Indexed SR8 – Old / New Status ...................................................... RO 7 Old / New Status (see SRB, SRC, SRD, SRE, GRE) 0 Old ..................................................... default 1 New 6 Interlace Scan Field 0 Odd ..................................................... default 1 Even 5 Reserved .........................................always reads 0 4 Command FIFO Empty 0 Empty ..........
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value SRE – Mode Control 1 (Old).............................................RW 7 Reserved ....................................... always reads 1 6 IRQ Polarity Select 0 Active High ............................................ default 1 Active Low 5 Configuration Port (SR0C) Select 0 Select Port 2 1 Select Port 1 .......................................... default 4 Reserved .........................................always reads 0 3 Memory Bus ...........
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Graphics Clock Synthesizer Control SR18 – VCLK1 Frequency Control 0 ..............................RW 7-0 VCLK1 Frequency Generator Numerator..... def=0 SR20 – Clock Synthesizer / RAMDAC Setup .................RW 7 Reserved ......................................... always reads 0 6 Multiplex Mode Sync Mechanism 0 Normal Mode..........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Graphics Signature Analyzer Registers Graphics Connector Control Registers SR21 – Signature Control..................................................RW 7 Signature Generator Enable 0 Disable (readback 0 indicates done) ...... default 1 Enable (readback 1 indicates busy) 6 Signature Source Select 0 TV / CRT ............................................... default 1 LCD 5-0 Bit Select ...............................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Graphics Playback Control Registers Graphics Second Playback Control Registers SR52-50 – Playback Color Key Data................................RW 23-16 Playback Color Key for True Color Mode 15-8 Playback Color Key for High Color Mode 7-0 Playback Color Key for 256 Color Mode SR62-60 – 2nd Playback Color Key Data .........................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Graphics Video Display Registers SR82-80 – Window 1 U-Plane FB Start Address ............RW 23-20 Reserved .........................................always reads 0 19-0 W1 U-Plane FB Start Address When operating in planar mode, this field defines the frame buffer starting address for the U-plane for the first live video window SR8C-8B – Window 2 Vertical Scaling Factor ...............RW 15 W2 Vertical Minify / Zoom Select 0 Zoom ..................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value SR96 – New Live Video Window Control 0.....................RW 7 W2 Horizontal Interpolation 0 Interpolation ........................................... default 1 Duplication 6 W1 Vertical Interpolation U and V Components 0 Enable..................................................... default 1 Disable This bit is effective only if window 1 vertical Y interpolation is enabled (CR8E[12] = 1) 5 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value SR9F – VBI Control ..........................................................RW 7 VBI Interrupt Status ........................................... RO 6 Reserved .........................................always reads 0 5 VBI Bit-8 4 VBI IV Bit-8 3 VBI Interrupt 0 Disable ................................................... default 1 Enable 2 VBI Enable 0 Disable ...................................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value SRAF-AE – Capture Row Byte Offset .............................RW 15 Reserved .........................................always reads 0 14 Capture Address Initial Control 13-0 Capture Row Byte SRBD – Dual View Mux Control......................................RW 7-3 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value SRD1-D0 – Window 2 UV Row Byte Offset ....................RW 15-14 Reserved .........................................always reads 0 13-0 W2 UV Plane Video Row Byte Offset (the bytes in a row) SRDB-DA – Window 2 V-Count Status............................RO 15-0 W2 V Count Status SRDD-DC – Dual View Control .......................................RW 15-11 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value VGA Extended Registers – Graphics Controller Indexed GRE – Old Source Segment Address ...............................RW 7-3 Reserved .........................................always reads 0 2-1 Source Segment Address Select............... default = 0 0 Reserved .........................................always reads 0 GRF – Miscellaneous Extended Function Control .........RW 7 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Power Management Registers GR20 – Standby Timer Control........................................RW 7 Timer Initialize & Enable 0 Enable Timer.......................................... default 1 Initialize and hold standby and DPMS timer 6-4 Timer Testing ....................................................... RO 3-0 Reserved .........................................always reads 0 GR22 – Power Management Control 2............................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GR23 – Power Status .........................................................RW 7 Power Management Pin Polarity (see GR21[7]) 6-5 Chip Power Status 00 Ready 01 Standby 10 Suspend 11 -reserved4 LCD Power Sequence Status 0 LCD power sequencing is not occurring at this time 1 LCD power sequencing is occurring at this time 3-2 Panel Power Sequencing 00 Fast panel power sequencing .................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GR26 – DPMS Control ......................................................RW 7-6 RAMDAC Internal Power Control 00 Normal ................................................... default 01 DAC off (used in LCD only mode) 10 Standby (DAC off, LUT in low power mode, I/O allowed to LUT). May be used in LUT bypass mode. 11 Suspend (DAC off, LUT access disallowed but LUT contents are preserved) 5-4 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GR28-27 – GPIO Control ..................................................RW 15-8 GPIO Direction 7-0 0 Read ..................................................... default 1 Write 7-0 GPIO Data 7-0........................................... default = 0 GR2F – Miscellaneous Internal Control..........................RW 7 PCLK Control 0 VGA Compatible ....................................default 1 PCLK equals VCLK 6 Reserved ............................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Scratch Pad Registers These registers are reserved for use by software. GR5A – Scratch Pad 0 .......................................................RW GR5B – Scratch Pad 1 .......................................................RW GR5C – Scratch Pad 2 .......................................................RW GR5D – Scratch Pad 3 .......................................................RW GR5E – Scratch Pad 4 ..........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value VGA Extended Registers – CRT Controller Indexed CRE – CRT Module Test...................................................RW 7 Extended Memory Access Above 256KB 0 Disable ................................................... default 1 Enable 6 VGA Misc Output Register (3C2) Write Protect 0 Writes to 3C2 Allowed .......................... default 1 Write Protect 3C2 5 CRT Start Address Bit-16 4-3 Reserved ........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value CR1F – Software Programming .......................................RW 7-4 Reserved .........................................always reads 0 3-0 Display Memory Size 0011 1MB 0111 2MB 1111 4MB 0100 8MB All other codes are reserved Memory size is automatically detected during system setup. CR29 – RAMDAC Mode...................................................RW 7 External DAC 0 Disable .....................................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value CR2B – Horizontal Parameter Overflow.........................RW 7-5 Reserved .........................................always reads 0 4 Horizontal Blank Start Bit-8.................... default = 0 3 Horizontal Retrace Start Bit-8 ............... default = 0 2 Horizontal Interlace Parameter Bit-8 .... default = 0 1 Horizontal Display Enable Bit-8 ............ default = 0 0 Horizontal Total Bit-8 .............................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value CR38 – Pixel Bus Mode .....................................................RW 7-6 Reserved .........................................always reads 0 5 Packed 24-Bit True-Color Mode 0 Disable ................................................... default 1 Enable 4 Standard VGA Mode in 64-Bit Configuration 0 Disable ................................................... default 1 Enable 3 True Color Mode 0 Disable ..........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value CR50 – Hardware Cursor Control...................................RW 7 Hardware Cursor Enable 0 Disable ...................................................default 1 Enable 6 Hardware Cursor Mode 0 MS Windows™ Compatible .................default 1 X11 Compatible 5 Hardware Cursor Color Control 3 0 Disable ...................................................default 1 Enable 4 Hardware Cursor Color Control 2 0 Disable ..................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Additional CRTC Extended Registers CR51 – Bus Grant Termination Control .........................RW 7-0 Bus Grant Termination Position This regiester is active if CR52[6] = 1 CR5E – Capture / ZV Port Control .................................RW 7 Capture Idle ..........................................................RO 6 Capture Command Port 0 Disable ....................................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value CR62 – Enhancement 0......................................................RW 7 Pause GE Operation (GEPAUSE) 0 Normal GE Operation ............................ default 1 Pause GE Operation 6 PCI Retry for GE (ENGERTRY) 0 Disable ................................................... default 1 Enable 5 Short Command (ENSHRT) 0 Disable ...................................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value video Y-component storage area, and W1-U (V) is the first live video U (V) -component storage area. In the following register definitions, a register with W1 (W2) indicates that this parameter is applicable to the first (second) live video window only.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value CR81-80 – Window 1 Horizontal Scaling Factor............RW 15 Horizontal Minify / Zoom Enable 0 Horizontal Zoom Enable........................ default 1 Horizontal Minify Enable CR89-86 – Window 1 Video Window Start.....................RW 31-28 Reserved ......................................... always reads 0 27-16 Video Window Vertical Start In pixel delays from the edge of VSYNC 15-12 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value CR8F-8E – Video Display Engine Flags ..........................RW 15 Planar Capture Mode 0 Planar 420 Capture................................. default 1 Planar 422 Capture 14 VSYNC Test / Graphics Engine Reset 0 Disable ................................................... default 1 Enable 13 Edge Recovery Algorithm Control 0 Disable ................................................... default 1 Enable 12 Window 1 Vertical Interpolation 0 Disable ...
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value CR9B – Video Display Status.........................................RWC 7 Capture Interrupt 0 Disable ................................................... default 1 Enable 6 Capture Interrupt Clear ................. Write 1 to Clear 5 VGA Vertical Blank..............................................RO 4 Capture Interrupt Status .....................................RO 3 Display Double Buffer Status ..............................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value CR9D – Capture Control 2................................................RW 7 Capture DTV / CCIR Format Select 0 CCIR ..................................................... default 1 DTV 6-4 Horizontal Filter Tap 0xx Bypass .................................................... default 100 2 Tap 101 3Tap 110 5 Tap 111 9 Tap 3 UV Swap 0 Normal ................................................... default 1 Swap 2 YUV Swap 0 Normal .......................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value CRA1-A0 – Capture Vertical Total..................................RW 15-11 Reserved .........................................always reads 0 10-0 Capture Vertical Total CRA3-A2 – Capture Horizontal Total .............................RW 15-9 Reserved .........................................always reads 0 8-0 Capture Horizontal Total CRA5-A4 – Capture Vertical Start ..................................RW 15-11 Reserved ...............................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value CRB1-B0 – Capture Horizontal Minify Factor...............RW 15 Reserved .........................................always reads 0 14-10 Planar Capture FIFO Level (for both U and V) 9-0 Capture Horizontal Minify Factor CRB3-B2 – Capture Vertical Minify Factor ...................RW 15 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Digital TV Control Registers VGA Extended Registers – CRTC Shadow CRD3-D0 – VGA / Digital TV Sync Control 1 ................RW 31-27 Reserved .........................................always reads 0 26-16 Vertical Data Load 15 VGA Slave Mode for DTV 0 Disable ................................................... default 1 Enable 14 H/V Data Load 0 Disable ...................................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value 3D Graphics Engine Registers This section describes how to program the PLE133 graphics engine for different operations. When the Setup Engine is to be used, the following steps should be taken to perform the drawing functions: • Software sets up the drawing environment. • Software issues a drawing command. • Software continuously sends triangles to Setup engine.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Drawing Bitblt - Frame Buffer to Frame Buffer A Note on CPU as the Source of Operation Blt operation may involve a pattern. If it does, and the pattern is stored in the frame buffer, the pattern parameters (P1, P2, P3) must also be set. The following registers must be set to provide the source and destination rectangles of blt: Ps1, Pd1, Ps2, and Pd2. These registers can be set in any order.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Geometry Primitives The PLE133 supports the following geometry primitives: line, and polygon. Each geometry primitive can be further modified for 3D, shading, and texture mapping. A different mechanism, called sequential loading, performs the geometry primitive set up operation. Loading Mechanism There are two ways to set up a geometry primitive, random loading and sequential loading.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Polygon General polygons can only be drawn by directly using the Rasterization Engine. In the PLE133, all polygons must be Ymonolithic, meaning, when walking from the vertex with minimal Y to the vertex with maximum Y, the Y coordinates of the vertices are monolithically increased.
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Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Triangle Synchronization Triangles can be drawn using the Polygon Mechanism described above. Additionally, triangles can also be drawn by using the Setup Engine if they meet certain criteria. Triangles and polygons can also be freely mixed in a drawing sequence.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Span Engine PS1, PS2, PD1, and PD2 are used in blt and text operations to define source and destination rectangles. GEbase + 0 - Parameter Source 1.....................................RW 31-28 Reserved .........................................always reads 0 27-16 Y-coordinate Parameter Source 1 Start High 12 bits of parameter source 1 starting address in Y coordinate 15-12 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Graphics Engine Core GEbase + 10 - Right View Display Base Address ...........RW 31 Right View Active 0 Inactive (use VGA style for display start address) .................................................. default 1 Active (use the base register address in this register for the display starting address) 30-24 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GEbase + 20 – Graphics Engine Status............................ RO Writing to this register resets the GE. 31 Bresenham Engine Status 0 Idle 1 Busy 30 Setup Engine Status 0 Idle 1 Busy 29 SP / DPE Status 0 Idle 1 Busy 28 Memory Interface Status 0 Idle 1 Busy (access for screen refresh doesn’t count) 27 Command List Processing Status 0 Idle 1 Busy 26 Block Write Status 0 Idle 1 Busy 25 Command Buffer Status 0 Not full 1 Full 24 Reserved .........
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GEbase + 24 – Graphics Engine Control ........................ WO 7 Reset 0 Normal operation ................................... default 1 Reset all internal registers and pointers. Reset is performed by setting this bit to 1 and then back to 0. 6-4 Reserved .........................................always reads 0 3-0 Debug Module Select ................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Graphics Engine Organization The PLE133 Graphics Engine consists of the following units: Setup Engine, Rasterization Engine, and Pixel Engine. These units are organized as follows: AGP Setup Engine Memory Interface The interfaces among the components are: • • AGP to Pixel Engine: Set drawing environment registers. AGP to Rasterization Engine: Set primitives: edge walking, slopes. AGP or Setup Engine: Set vertices, culling info.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Setup Engine Registers GEbase + 30 – Setup Engine Primitive Attribute ...........RW 31 Z Parameter 0 Absent .................................................... default 1 Present (Setup Engine calculates Z slope) 30 Texture Parameter 0 Absent .................................................... default 1 Present (SE calculates Z slope) 29 Perspective Factor Parameter 0 Absent ....................................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GEbase + 3C –Setup Engine Primitive Type.................. WO Writing to this register signals the Graphics Engine to begin sequential loading. The engine will interpret the contents of this register and the Primitive Attribute register to decide the amount and types of parameters to expect. Like vertices, there is a FIFO for Triangle Attributes. The queue has three entries. Writing to this register adds it to the queue.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Rasterization Engine Registers The major responsibilities of the Rasterization Engine are: • • • • Receive data from host: Set registers, sequential loading of parameters. Edge walking: Generate end points of polygon edges or pixels on a line. Interpolation: Calculate values such as texture coordinates on a polygon / line. Perspective correction: Perform perspective correction.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GEbase + 30 – RE Primitive Attribute.............................RW 31 Z Parameter 0 Absent .................................................... default 1 Present (Rasterization Engine calculates Z slope) 30 Texture Parameter 0 Absent .................................................... default 1 Present (RE calculates texture info) 29 Perspective Factor Parameter 0 Absent ....................................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GEbase + 3C – RE Primitive Type .................................. WO Writing to this register signals the Graphics Engine to begin sequential loading, but doesn’t cause anything to be drawn.. The engine will interpret the contents of this register and decide the amount and types of parameters to expect. 31-30 Loading Target 00 Rasterization Engine. Send bits 19-0 to the RE. Sequential loading data will also be sent to the RE......................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Bresenham Edge Parameters Bresenham Edge parameters describe an edge of a primitive or a line. DDA Edge Parameters DDA Edge parameters describe an edge of a primitive or a line. DoubleWord 0 – Start Coordinates 31-16 Start YS1 Starting coordinate of the line in the Y direction (signed 12.4 number). The fractional part must be 0. This parameter is ignored in minor edges.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Color Parameters Color parameters are used for Gouraud shading. They consist of starting values, incremental along the X and Y axis. In flat color mode, this parameter only has the starting value. DoubleWord 0 – Initial Values 31-24 Initial Alpha Value Initial Alpha value on main edge (left edge of trapezoid or long edge of triangle). Unsigned integer.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Texture Coordinate Parameters Texture parameters are used for texture mapping. They consist of starting values, incremental along the X and Y axis. DoubleWord 0 – Initial U Value 31-0 Initial U Value Initial U value on main edge (left edge of trapezoid or long edge of triangle). Signed 16.16 integer. DoubleWord 1 – Initial U Value 31-0 Initial U Value Initial U value on main edge (left edge of trapezoid or long edge of triangle). Signed 16.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Specular / Fog Start Value The specular / fog start value is used for specular shading or fogging. DoubleWord 0 – Start Value 31-24 Initial Fog Value Initial Fog value on main edge (left edge of trapezoid or long edge of triangle). Unsigned integer. 23-16 Initial Red Value Initial Red value on main edge (left edge of trapezoid or long edge of triangle). Unsigned integer.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Data from the Host Pixel Engine Registers The major responsibilities of the Pixel Engine are to perform per-pixel operations and to control data flow and its sequence. The Pixel engine interfaces to the Rasterization Engine and the host to accept data. It also interfaces to the Memory Interface to access video memory. Inside the Pixel Engine, there are several blocks: the Span Engine, the Data Path, and the Texture Engine.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GEbase + 44 – Drawing Command ..................................RW Writing to the Drawing Command register starts a drawing operation. When this register is set, the drawing environment registers and memory interface registers are locked in. Any change to these registers will not affect this drawing operation. Furthermore, the Pixel Engine will not accept any data from the host or from the Rasterization Engine without a drawing command.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GEbase + 48 – Raster Operation (ROP) ..........................RW 31-8 Reserved .........................................always reads 0 7-0 ROP3 Code Revision 1.82 October 22, 2001 -127 GEbase + 4C – Z Function ................................................RW 31 Z-Bias 0 Disable 1 Enable 30-17 Reserved .........................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GEbase + 50 – Texture Function ......................................RW 31-22 Maximum U 21-12 Minimum U 11-5 Reserved .........................................always reads 0 4 Mask 0 Disable 1 Enable 3-2 Texture Alpha 00 Texel alpha 01 Source alpha 10 Modulated alpha: texel alpha x source alpha 11 -reserved1-0 Texture Color 00 Texel color 01 Source color 10 Modulated color: texel color x source color 11 -reserved- GEbase + 54 – Clipping Window 0.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GEbase + 6C – Pattern and Style .....................................RW 31 Pattern Color Expansion 0 Disable ................................................... default 1 Enable 30 Pattern Transparency 0 Opaque ................................................... default 1 Transparent 29 Pattern Size 0 8 x 8 pixels ............................................. default 1 32 x 32 pixels (mono only) 28 Pattern Register Segment 0 Low Segment ..........
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GEbase + 7C – Alpha .........................................................RW 31-16 Reserved .........................................always reads 0 15-8 Source Constant Alpha 7-0 Destination Constant Alpha GEbase + 84 – Bit Mask.....................................................RW 31-0 Bit Mask One bits indicate that the corresponding color bit will not be written to the frame buffer. Revision 1.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Texture Engine Registers The texture Engine handles texture access and filtering. It is controlled by the Span Engine. It accepts texture coordinates from the Rasterization Engine, generates and passes addresses to the Memory Interface, accepts raw texel data from the Memory Interface, does filtering, and passes the results to the Data Path. GEbase + A0 – Texture Control .......................................
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value GEbase + A4 – Texture Color ...........................................RW 31-24 Alpha Constant alpha value when there is no alpha in the texture format 23-0 Texture Color Key Texture transparency color (888 RGB) GEbase + A8 – Texture Palette Data............................... WO 31-16 Texel n+1 15-0 Texel n An internal counter is used in loading the texture palette. Writing to the Texture register (GEbase+A0) resets the counter to 0.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Memory Interface Registers The registers in this group include stride and buffer base address registers for frame buffer control. There are three base addresses: source base address (added to blt source), destination base address (added to color destination), and Z base address (added to Z addresses). There are 9 texture base registers for up to 9 levels of MipMaps: level 0 (1:1 map) up to level 8 (smallest).
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value FUNCTIONAL DESCRIPTIONS Graphics Controller Power Management Power Management Registers The PLE133 Graphics Controller power mangement feature set complies with AGP and PCI power management requirements.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Table 13. Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes 0 85 oC 1 Storage temperature -55 125 oC 1 Input voltage -0.5 VRAIL + 10% Volts 1, 2 Output voltage -0.5 VRAIL + 10% Volts 1, 2 TC Case operating temperature TS VIN VOUT Note 1: Stress above the conditions listed may cause permanent damage to the device.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value Power Characteristics TC = 0-85oC, VRAIL = VCC +/- 5%, VCORE = 2.5V +/- 5%, GND=0V Table 15.
Technologies, Inc. VT8601A Apollo PLE133 Delivering Value MECHANICAL SPECIFICATIONS 30.00 R EF 4.00*45º (4X) 26 25 24 23 22 21 Chipset Name 20 19 18 17 15 14 Apollo PLE133 13 12 11 VT8601A YYWWCE TAIWAN LLLLLLLLL C M 10 Date Code Year (YY) Date Code Week (WW) Country of Assembly Chip Revision (CE) Lot Code (L) 30.