Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 Signal Connectivity and Design Checklist
81
Technologies, Inc.
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5.3 "Super South" South Bridge Controller
The connectivity for each signal of VT82C686A South Bridge is listed in Table 5-2. Motherboard designers can use this table as a
quick reference to review their schematics. Some pins have been repeatedly described for different functions in different sub-
tables, please be careful in using the following table.
Table 5-2. VT82C686A South Bridge Connectivity
PCI BUS INTERFACE
Signal Name I/O Connection
PCLK I Connect to the PCI clock output of an external Clock Synthesizer.
AD[31:0] IO Connect to VT82C694X and PCI slots.
C/BE[3..0]# IO Connect to VT82C694X and PCI slots.
FRAME# IO Connect between VT82C694X, PCI slots, and VT82C686A. 10K ohm pull-up to VCC.
IRDY# IO Same as the above.
TRDY# IO Same as the above.
STOP# IO Same as the above.
DEVSEL# IO Same as the above.
SERR# I Same as the above.
PAR IO Connect to VT82C694X and PCI slots.
IDSEL I Connect to AD18 with a series 100 ohm resistor.
PIRQ[D:A]# I Connect to pins INT[D..A]# of each PCI slot as follows:
PIRQA# PIRQB# PIRQC# PIRQD#
PCI slot 1 INTA# INTB# INTC# INTD#
PCI slot 2 INTB# INTC# INTD# INTA#
PCI slot 3 INTC# INTD# INTA# INTB#
PCI slot 4 INTD# INTA# INTB# INTC#
Connect one of these pins to pin INTA# of VT82C694X.
PREQ# O Connect to VT82C694X.
PGNT# I Connect to VT82C694X.
PCKRUN# IO Connect to ground with a series 100 ohm resistor if the function is not applied.
CPU INTERFACE
Signal Name I/O Connection
A20M# OD Connect to CPU. 4.7K ohm pull-up to VCC3.
CPURST OD Same as the above.
IGNNE# OD Same as the above.
INIT OD Same as the above.
INTR OD Same as the above.
NMI OD Same as the above.
SMI# OD Same as the above.
STPCLK# OD Same as the above.
FERR# I Same as the above.
SLP#/GPO7 OD Connect to Slot-1 CPU only if the function is applied. 4.7K ohm pull-up to VCC3.