Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 Signal Connectivity and Design Checklist
80
Technologies, Inc.
We ConnectWe Connect
CLOCK AND RESET CONTROL
Signal Name I/O Connection
HCLK I Connect to the CPU clock output of the system clock synthesizer.
DCLKO O Connect to the SDRAM clock input of the system clock synthesizer.
DCLKWR I Connect to the SDRAM clock output of the system clock synthesizer.
GCLKO O Connected to the AGP clock input of the AGP slot through a 22 ohm resistor.
GCLK I Connected to the GCLKO of VT82C694X through a 22 ohm resistor.
PCLK I Connect to the PCI clock output of the system clock synthesizer.
RESET# I Connected to VT82C686A through a 74F240 inverter.
PWROK I Connect to VT82C686A and Power Good circuitry.
GCKRUN# / GPAR O/IO Connected to VT82C686A and the system clock synthesizer if the function is applied.
SUSCLK I Connect to VT82C686A. 10K ohm pull-up to VCC3.
SUSTAT# I Connect to VT82C686A. 10K ohm pull-up to VCC3.
CPURSTI# I Connect to the MUX circuitry of the CPU strapping signals. 10K ohm pull-up to VCC3.
CLKRUN# I Connected to VT82C686A and the system clock synthesizer if the function is applied.
Otherwise, connect to VT82C686A then through a 100 ohm serial resistor to ground.
MISCELLANEOUS
Signal Name I/O Connection
VCC P Connect to VCC3.
GND P Connect to ground.
VCCA P Connect to VCC3.
GNDA P Connect to ground.
VSUS P Connect to 3.3V standby power source.
VCCQ P Connect to VDDQ (1.5V or 3.3V).
VCCQQ P Connect to VDDQ (1.5V or 3.3V).
GNDQQ P Connect to ground.
VTT P Connect to GTL threshold voltage (1.5V).
GTLREF P Connect to GTL Buffer reference voltage (1.0V) circuitry.
AGPREF P Connect to AGP reference voltage (1.32V) circuitry.
TESTIN# I 8.2K ohm pull-up to VCC3.