Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 70 Motherboard Design Guidelines
Technologies, Inc.
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2.5.7 Suspend to DRM
Power-on-suspend (POS), Suspend-to-RAM (STR) and Suspend-to-Disk (STD) or so called Soft-off are three different suspend
states supported by the VT82C686A. These suspend functions are implemented not only in a notebook PC design but also in a
desktop PC design. And the STR function is specially described in this section.
2.5.7.1 Suspend DRAM Refresh
During STR state, power is removed from most of the system except the system DRAM and the power management section of
VT82C686A. Power is supplied to the suspend refresh logic of the VT82C694X (VSUS) and the suspend logic of the
VT82C686A (VCCSUS). One additional suspend status indicator (SUSST1#) is provided to inform the north bridge and the rest
of the system of the processor and system suspend states. SUSST1# is asserted to tell the north bridge to switch to “Suspend
DRAM Refresh” mode. SUSST1# is asserted when the system enters the suspend state or the processor enters the suspend (C3)
state. SUSST1# is connected to the north bridge to switch between normal and suspend-DRAM-refresh modes The Suspend
DRAM Refresh application circuit is shown in Figure 2-62.
DIMM2
(Group A)
111
27
27
48
48
48
DIMM1
(Group A)
VT82C694X
(North Bridge)
DIMM3
(Group B)
VT82C686A
(South Bridge)
Main Memory
SUSST1SUSSAT#
AD4 T17
CKE0/FENA
CKE1/GCKE#
CKE2/CSB6#
CKE3/CSB7#
CKE5/CSA#
CKE4/CSA6#
SRASB#
SCASB#
SWEB#
10K
ohm
3V3SB
AF24
AC23
AD23
AE24
AF23
AC22
63
128
63
128
63
128
115
111
115
111
115
27
SRASA#
SCASA#
SWEA#
AF164
AE12
AF12
AC12
AB13
AA17
AC4
VSUS
3V3SB
V_DIMM
V_DIMM
V_DIMM
V_DIMM
R16
VCCSUS
3V3SB
L16
VCCSUS
Notes:
1. During STR state, all VT82C694X and VT82C686A signals are powered by 3.3V suspend power.
2. Main memory is also powered by 3.3V suspend power through V_DIMM.
Figure 2-62. Suspend DRAM Refresh Application Circuit
Suspend DRAM refresh state (self refresh mode for DRAM modules) is entered by having CKE[0:5], SRAS[A:B}#, SCAS[A:B]#
held low with SW[A:B]# high at the rising edge of the SDRAM clock.