Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 67 Motherboard Design Guidelines
Technologies, Inc.
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Dual channel master mode PCI supports four Enhanced IDE devices. The transfer rate for each device can support up 33 MB/sec
to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-33 interface. Transmission line effects and signal crosstalk
emerge in the IDE related signals. To eliminate ringing and reflection caused by the transmission line effect, trace length and
impedance match must be taken into account. An example IDE layout is shown in Figure 2-59. Recommended layout rules for
both primary and second IDE ports are listed below:
• The trace attribute of all primary IDE signals is in a minimum of 6 mils wide and 9 mils between two adjacent traces. The
recommended trace length is less than 6 inches.
• All ATA signals in Figure 2-59 require series termination resistors. The series resistors (R
A
) should be placed within 1
inch of the VT82C686A chip. The series resistors (R
B
) should be placed within 1 inch of the primary IDE connector.
• Signal DD7 needs a 10K pull-down on the VT82C686A chip side of series termination
• Signal DREQ needs a 5.6K pull-down on the connector side of the series termination
• Signal IRQ14 (or IRQ15) needs a 10K pull-down or pull-up (preferred) on the connector side of the series termination
• Signal IORDY# needs a 1K pull-up on the connector side of the series termination
• Pin 28 of the IDE connectors should be tied to ground with a 470 ohm serial resistor.
• It is recommended to layout the following signals to each IDE connector in equal length. They are signals DD[15..0],
IOR#, IOW#, and IORDY#.
VT82C686A
(South Bridge)
DD[15..0]
PDDREQ
PDIOW#
PDIOR#
PIORDY#
PDDACK#
IRQ14
PDA[2..0]
PDCS3#
PDCS1#
Trace length (L1) < 6"
Primary
IDE
Connector
1K ohm
5.6K ohm
10K ohm
10K ohm
(note 1)
VCC
DD[15..0]
DREQ
IOW#
IOR#
IORDY#
DACK#
IRQ14
DA[2..0]
CS3#
CS1#
IDERST#
VCC
Note 1: 10K ohm resistor pull-down for DD7 only
L1
L2
Trace length (L2) < 6"
82 ohm
33 ohm
R
A
R
B
21
27
31
1
29
25
23
38
33
470 ohm
28
SPSYNC:CSEL
RSTDRV
F04
Figure 2-59. IDE Interfaces Layout Guidelines