Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 50 Motherboard Design Guidelines
Technologies, Inc.
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Note: MAB[14:0]# represents MAB[14:11]#, MAB10 and MAB[9:0]#.
VT82C694X
(North Bridge)
2" < L1 < 3.5"
DIMM2 DIMM1
0.4" < L2 < 0.5"
MAA[14:0]
MD[63:0]
CASA[7:0]#
MECC[7:0]
SWEA#
SRASA#
SCASA#
SWEB#
SRASB#
SCASB#
RASA[1:0]#
RASB[1:0]#
RASA[5:4]#
RASB[5:4]#
RASA[3:2]#
RASB[3:2]#
No Connet
MAB[14:0]#
RASA[7:6]#
RASB[7:6]#
2" < L3 < 4"
CASB[5,1]#
No Connet
No Connet
No Connet
No Connet
(Group A)
Figure 2-42. Daisy Chain Routing for Two-DRAM DIMM Slots
2.4.2.2 DRAM Reference Layout
Maintaining DRAM trace length less than 4 inches is required to fulfill 133 MHz DRAM timing requirements. A placement
example of the VT82C694X chip and 3 DIMM slots is shown in Figure 2-43. The VT82C694X chip is located at the top of the
middle of 3 DIMM slots. The distance between the chip and the closest DIMM slot (DIMM3) is 0.55 inch. The distance between
the centers of two adjacent DIMM slots is 0.4 inch.
VT82C
694X
0.55"
DIMM1
DIMM2
DIMM3
0.4"
Figure 2-43. DRAM Placement for 133MHz Timing Consideration