Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 45 Motherboard Design Guidelines
Technologies, Inc.
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A layout example for the remaining control signals between the VT82C686A chip and the Slot-1 CPU is shown in Figure 2-37.
Slot-1
CPU
VT82C686A
(South Bridge)
FERR#
CPURST
SLP#
SMI#
STOPCLK#
FERR#
SLP#
SMI#
STOPCLK#
330
ohm
Layout these traces
as short as possible
VCC2_5
No Connect
INIT INIT
Figure 2-37. Layout Example of Control Signal from South Bridge to Slot-1 CPU
No sharing circuitry is required in an S-Spec Socket-370 system design because the S-Spec Socket-370 CPU runs at marked ratio
only. A layout example for all control signals between the VT82C686A chip and the Socket-370 CPU is shown in Figure 2-38.
Currently, the voltage level of VCC_CMOS is 2.5V.
Socket-370
CPU
VT82C686A
(South Bridge)
FERR#
CPURST
SLP#
SMI#
STOPCLK#
FERR#
SLP#
SMI#
STOPCLK#
330
ohm
Layout these traces as short as possible
VCC_CMOS
No Connect
INIT INIT
A20M#
IGNNE#
INTR(LINT0)
NMI(LINT1)
A20M#
IGNNE#
INTR
NMI
Figure 2-38. Layout Example of Control Signal from South Bridge to Socket-370 CPU
The layout guidelines for these signals from the Slot-1 or Socket-370 CPU to the south bridge (VT82C686A) are listed below.
• Each south bridge Open Drain (OD) output control signal to the CPU needs a 150 ~ 450 ohm pull-up which should be
placed as close to the VT82C686A chip as possible.
• A minimum of 5 mils in width and a minimum of 10 mils in spacing are sufficient for good signal quality.
• No specific limitation of the trace length for these control signals is required.