Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 44 Motherboard Design Guidelines
Technologies, Inc.
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2.4.1.3 CPU Host Interface to South Bridge
The host control signals from the Slot-1 or Socket-370 CPU to the south bridge (VT82C686A) are listed in Table 2-9. Except for
FERR#, all signals are open drain (OD). 2.5V pull-ups are required for those open drain signals on the VT82C686A chip side.
Table 2-9. Host Control Signals to South Bridge
South Bridge -- CPU
Signal Name I/O Description
A20M# OD A20 Mask
CPURST OD CPU Reset
FERR# I Numerical Coprocessor Error
IGNNE# OD Ignore Numerical Error
INIT OD Initialization
INTR OD CPU Interrupt
NMI OD Non-Maskable Interrupt
SLP# OD Sleep
STPCLK# OD Stop Clock
SMI# OD System Management Interrupt
In a Slot-1 system design, pins A20M#, IGNNE#, INTR (LINT0) and NMI (LINT1) are shared with the external CPU clock ratio
straps. The schematic for this pin sharing is shown in Figure 2-36. These pins strap the setting of the CPU clock ratio during reset
and two clocks beyond the end of the RESET# pulse. Afterwards, the functionality of these signals will work as their names are
defined. (Note: This ratio select logic is also required in the Q-Spec Socket-370 system design.)
VT82C686A
(South Bridge)
Slot-1
CPU
A20M#
IGNNE#
INTR
NMI
A20M#
IGNNE#
INTR(LINT0)
NMI(LINT1)
U1
A1
A8
A7
A6
A5
A4
A3
A2
Y1
Y8
Y7
Y6
Y5
Y4
Y3
Y2
OE0#
11
12
13
14
15
16
17
18
1
19
9
8
7
6
5
4
3
2
LVT244
OE1#
NC7S04
LVT07
4.7K
ohm
U2
JUMPER
CRESET#
2
87
65
43
1
VCC3
VCC2_5
U3
10K
ohm
VCC3
20
VCC3
From
VT82C694X
330
ohm
Note: LVT244, LVT07 and NC7S04 operate at the 3.3 volt interface.
Figure 2-36. Schematic Example for Slot-1 CPU Internal/External Clock Ratio Pin Sharing