Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 38 Motherboard Design Guidelines
Technologies, Inc.
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2.3.2.9 Clock Trace Length Calculation
The calculation is based on the recommended placements shown in sections 2.2.1 and 2.2.2. A different component placement
may result in a different calculation for the clock trace length.
CPU Clock Trace Length Calculation for Slot-1 System
Before routing any other signals on the board, pre-route every CPU clock trace from the system clock synthesizer to the Slot-1
CPU (CPUCLK) and North Bridge (HCLK) as short as possible. All high frequency clock alignment will be on the basis of the
longest one (usually CPUCLK around 3700 mils). Please refer to the component placements in figures 2-3 and 2-4. A calculation
example is shown below.
Clock Trace Shortest
Length
Desired
Length
Allowable
Difference
Allowable
Range
Clock chip à CPU L
CPU
L
CPU
- 1"~9"
Clock chip à VT82C694X (NB) L
NB
L
CPU
+ 3"
0.5" 4"~12"
Note: Here, the 3" represents the estimated trace length added into HCLK for CPU clock alignment.
CPU Clock Trace Length Calculation for Socket-370 System
Before routing any other signals on the board, pre-route every CPU clock trace from the system clock synthesizer to the Socket-
370 CPU (CPUCLK) and North Bridge (HCLK) as short as possible. All high frequency clock alignment will be on the basis of
the longest one (usually HCLK around 5500 mils). Please refer to the component placements in figures 2-5 and 2-6. A calculation
example is shown below.
Clock Trace Shortest
Length
Desired
Length
Allowable
Difference
Allowable
Range
Clock chip à CPU L
CPU
L
NB
0.5" 1"~9"
Clock chip à VT82C694X (NB) L
NB
L
NB
- 1"~9"
SDRAM Clock Trace Length Calculation
Pre-route SDRAM clock traces (SDCLK0~SDCLK11) from the system clock synthesizer to the DIMM slots as short as possible.
The length of all SDRAM clocks will be based on the longest one (L
SD
). The length of DCLKWR (L
DIN
) should be the same as
that of the SDCLKs. The DCLKO clock trace should be as short as possible. A calculation example is shown below.
Clock Trace Shortest
Length
Desired
Length
Allowable
Difference
Allowable
Range
Clock chip à SDCLK[15:0] L
SD
L
SD
0.5" 1"~4"
DCLKWR (Clock chip à NB) L
DIN
(assume < L
SD
+3")
L
SD
+ 4.5"
0.5" 4"~7"
DCLKO (NB à Clock chip) L
DOUT
L
DOUT
- 1"~9"
Note: Here, the 4.5” represents the estimated trace length added into DCLKI for SDRAM clock alignment.