Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 37 Motherboard Design Guidelines
Technologies, Inc.
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2.3.2.7 PCI Clock Signals
Layout recommendations for the PCI clocks are shown in Figure 2-29. Typically, 22 ohm series terminations are recommended
for all PCI clocks. A typical 22 pF bypass capacitor is also required for each PCI clock. Depending on how the system is
designed, the value of the bypass capacitors for the PCI clocks may vary. For clock alignment considerations, trace lengths of all
PCI clocks should match the longest one.
System
Clock
Synthesizer
VT82C694X
(North Bridge)
NPCLK
SPCLK
P
C
I
1
VT82C686A
(South Bridge)
PCLK0
PCLK3
PCLK2
PCLK1
0 ~ 33
ohm
10 ~ 33
pF
P
C
I
4
P
C
I
3
P
C
I
2
L
5
+ 3" (L
NB
)
L
5
+ 3" ( L
SB
)
L
5
( L
2
)
L
5
( L
1
)
L
5
( L
3
)
PCLK4
P
C
I
5
L
5
( Assume L
5
> L
1
, L
2
and the rest )
L
5
( L
4
)
Figure 2-29. PCI Clock Layout Recommendations
2.3.2.8 Miscellaneous Clock Signals
22 ohm series terminations are recommended for clock signals such as the USB clock (48 MHz), Super I/O clock (typically 24
MHz), IOAPIC clock (14.31818MHz, 2.5V interface) and reference clock (14.31818 MHz, 3.3V interface) which are generated
from the system clock synthesizer. The trace width for the clocks above should be at least 15 mils. To reduce crosstalk impact,
trace spacing between these clocks and other signals should be maintained at a minimum of 15 mils. In order to maintain the
clock signal quality, the trace length of these clock signals, especially USBCLK, should be as short as possible or less than 9
inches.